Semiconductor memory device having potential control circuit

  • US 20030174570A1
  • Filed: 08/19/2002
  • Published: 09/18/2003
  • Est. Priority Date: 03/12/2002
  • Status: Active Grant
First Claim
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1. A semiconductor memory device comprising:

  • a plurality of word lines arranged in a row direction;

    a plurality of bit lines arranged in a column direction;

    a plurality of memory cells arranged in the row direction and the column direction;

    a plurality of potential supply lines connected to a plurality of corresponding bit lines among said plurality of bit lines, respectively; and

    a potential control circuit supplying a plurality of predetermined potentials corresponding to said plurality of bit lines through said plurality of potential supply lines, respectively, wherein the plurality of memory cells arranged in said row direction are connected in series, and gates thereof are connected to the word line of said plurality of word lines arranged in the same row direction, and each of said plurality of bit lines is connected to said plurality of memory cells arranged in the two adjacent columns.

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