Dynamic memory allocation between inbound and outbound buffers in a protocol handler

• US 20030177293A1
• Filed: 03/12/2002
• Published: 09/18/2003
• Est. Priority Date: 03/12/2002
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Schuh, Brian J., Bunce, Robert M., Bilak, Mark R., Parker, Steven C.
• Granted Patent: US 6,877,048 B2
• Time in Patent Office: Days
• US Class Current: 710/56
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Claims

1. An apparatus for processing data packets employing dynamic memory allocation between inbound and outbound memory buffers, comprising:

a first memory buffer for receiving incoming data packets;

means for generating outgoing data packets from said received incoming data packets or from a host system interface;

a second memory buffer for transmitting said outgoing data packets generated; and

means for dynamically allocating memory between said first memory buffer and said second memory buffer for optimally receiving said incoming data packets and for storing and transmitting said outgoing data packets.

2. The apparatus of claim 1, further comprising:

an inbound processor, with logic, associated with said first memory buffer, wherein said first memory buffer is dedicated to said inbound processor; and

an outbound processor, with logic, associated with said second memory buffer, wherein said second memory buffer is dedicated to said outbound processor.

3. The apparatus of claim 1, further comprising a processor, with logic, wherein a portion of said processor is dedicated to said first memory buffer and another portion of said processor is dedicated to said second memory buffer.

4. The apparatus of claim 2, wherein said first memory buffer and said second memory buffer each is divided into blocks and said blocks are sized to be smaller than a maximum frame size of the data packet to be processed.

5. The apparatus of claim 4, wherein said blocks are managed as one of a free list or as a linked list of blocks.

6. The apparatus of claim 2, further comprising a processor thread for managing said blocks and for determining an amount of free space available in said inbound memory buffer and said outbound memory buffer.

7. The apparatus of claim 5, further comprising an interprocessor communication path for allowing equal access to said inbound memory buffer and said outbound memory buffer.

8. The apparatus of claim 1, further comprising a means for throttling data frame reception rate in the event insufficient memory exists in said incoming memory buffer or in said outgoing memory buffer.

9. The apparatus of claim 1, wherein said dynamic memory allocation means includes:

a means to allocate a portion of said inbound memory buffer for a future frame reception; and

a means to allocate a portion of said outbound memory buffer for a future frame transmission.

10. The apparatus of claim 9, further comprising a means to deallocate any allocated memory blocks for reuse.

11. A method of processing data packets employing dynamic memory allocation between inbound and outbound memory buffers, said method comprising the steps of:

receiving incoming data packets via a first memory buffer;

generating outgoing data packets from said received data packets or from a host system interface;

transmitting said outgoing data packets generated via a second memory buffer; and

dynamically allocating memory between said first memory buffer and said second memory buffer for optimally receiving said incoming data packets and for storing and transmitting said outgoing data packets.

12. The method of claim 11, further comprising the steps of providing an inbound processor, with logic, wherein said first memory buffer is dedicated to said inbound processor, and providing an outbound processor, with logic, wherein said second memory buffer is dedicated to said outbound processor, and wherein the memory in said inbound memory buffer and said outbound memory buffer is sharable.

13. The method of claim 11, further comprising the step of providing a processor, with logic, wherein a portion of said processor is dedicated to said first memory buffer and another portion of said processor is dedicated to said second memory buffer.

14. The method of claim 12, further comprising the steps of dividing said inbound memory buffer and said outbound memory buffer into blocks and said blocks are sized to be smaller than a maximum frame size of the data packet to be processed.

15. The method of claim 14, further comprising the step of managing said blocks as one of a free list or as a linked list of blocks.

16. The method of claim 14, further comprising the steps of managing said blocks using a processor thread for determining an amount of free space available in said inbound memory buffer and in said outbound memory buffer.

17. The method of claim 12, further comprising the step of allowing equal access to said inbound memory buffer and said outbound memory buffer using an interprocessor communication path.

18. The method of claim 12, further comprising the step of throttling data frame reception rate in the event insufficient memory exists in said incoming memory buffer or said outgoing memory buffer.

19. The method of claim 11, wherein the dynamic memory allocation is accomplished by a process involving the steps:

allocating a portion of said inbound memory buffer for a future frame reception; and

allocating a portion of said outbound memory buffer for a future frame transmission.

20. The method of claim 19, further comprising the step of deallocating any allocated memory blocks for reuse.