Memory structures

• US 20030185034A1
• Filed: 04/02/2002
• Published: 10/02/2003
• Est. Priority Date: 04/02/2002
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Stasiak, James, Van Brocklin, Andrew L., Fricke, Peter, Koll, Andrew
• Granted Patent: US 6,967,350 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices

Abstract

A memory structure that includes a first electrode, a second electrode, a third electrode, a control element of a predetermined device type disposed between the first electrode and the second electrode, and a memory storage element of the predetermined device type disposed between the second electrode and the third electrode. The memory storage element has a has a cross-sectional area that is greater than a cross-sectional area of the control element.

Claims

1. A memory structure comprising:

a first electrode;

a second electrode;

a third electrode;

a memory storage element of a predetermined device type disposed between said third electrode and said second electrode, said memory storage element having a memory storage element cross-sectional area and configured for predictable breakdown as a memory storage element;

a control element of said predetermined device type disposed between said second electrode and said first electrode, said control element having a control cross-sectional area and configured as a control element for said memory storage element; and

said control element cross-sectional area being larger than said memory storage element cross-sectional area.

2. The memory structure of claim 1 wherein said memory element and said control element comprise tunnel junction devices.

3. The memory structure of claim 1 wherein said control element comprises an oxide of said first electrode, and wherein said memory storage element comprises an oxide of said second electrode.

4. The memory structure of claim 1 wherein said control element comprises an oxide of said first electrode, and wherein said memory tunnel junction region comprises an oxide of said third electrode.

5. The memory structure of claim 1 wherein said control element and said memory storage element are substantially co-planar.

6. The memory structure of claim 1 wherein said control element and said memory storage element are horizontally separated.

7. The memory structure of claim 1 wherein said control element and said memory storage element are vertically separated.

8. An integrated circuit including the memory structure of claim 1.

9. A memory carrier including the memory structure of claim 1.

10. An electronic device configured to receive the memory carrier of claim 9.

11. An electronic device including the memory structure of claim 1.

12. The memory structure of claim 1 wherein:

said first electrode comprises a first conductor having a top surface;

said third electrode comprises a second conductor horizontally adjacent said first conductor and having a top surface;

said control element is disposed on said top surface of said first conductor; and

said memory storage element is disposed on said top surface of said second conductor.

13. The memory structure of claim 12 wherein said first conductor and said second conductor are substantially co-planar.

14. The memory structure of claim 12 wherein said control element comprises an oxide of said first conductor, and wherein said memory storage element comprises an oxide of said second conductor.

15. The memory structure of claim 12 wherein said control element comprises an oxide different from an oxide of said first conductor.

16. The memory structure of claim 12 wherein said memory storage element comprises an oxide different from an oxide of said second conductor.

17. The memory structure of claim 1 wherein:

said second electrode comprises a conductive tub having a base and a rim that are vertically separated;

said first electrode comprises a first memory selection conductor vertically adjacent said base of said conductive tub;

said control element is disposed between said first memory selection conductor and said base of said conductive tub;

said third electrode comprises a second memory selection conductor vertically adjacent a portion of said rim of said conductive tub; and

said memory storage element is disposed between said second memory selection conductor and said rim of said conductive tub.

18. The memory structure of claim 1 wherein:

said third electrode comprises a truncated conductive cone having a rim edge;

said third electrode comprises a conductor adjacent said rim edge; and

said memory storage element is disposed between said rim edge and said conductor.

19. The memory structure of claim 1 wherein:

said third electrode comprises a conductive pillar;

said second electrode comprises a conductor laterally adjacent said conductive pillar; and

said memory storage element is disposed between said conductive pillar and said conductor.

20. The memory structure of claim 19 wherein said conductor comprises a conductive plate laterally adjacent said conductive pillar.

21. The memory structure of claim 19 wherein said conductor comprises a conductive block laterally adjacent said conductive pillar.

22. The memory structure of claim 1 wherein:

said third electrode comprises a conductive tub;

said second electrode comprises a conductor laterally adjacent said conductive tub; and

said memory storage element is disposed between said conductive tub and said conductor.

23. The memory structure of claim 22 wherein said conductor comprises a conductive plate laterally adjacent said conductive tub.

24. The memory structure of claim 22 wherein said conductor comprises a conductive block laterally adjacent said conductive tub.

25. The memory structure of claim 1 wherein:

said third electrode comprises a conductive structure having a vertical extent;

said second electrode comprises a non-horizontal conductive panel laterally adjacent said conductor and a horizontal conductive plate connected to said conductive panel;

said first electrode comprises a conductor laterally adjacent said conductive panel;

said memory storage element is disposed between an edge of said horizontal plate and said conductive structure; and

said control element is disposed between said conductor and said conductive panel.

26. The memory structure of claim 25 wherein said conductive structure comprises a conductive pillar.

27. The memory structure of claim 25 wherein said conductive structure comprises a conductive tub.

28. The memory structure of claim 25 wherein:

said conductor comprises an elongated conductive wall having a vertical extent;

said conductive panel is laminarly adjacent said elongated conductive wall; and

said control element is disposed between said conductive panel and said elongated conductive wall.

29. A memory structure comprising:

a conductive structure having a vertical extent;

a first memory storage element of a predetermined device type and a first control element of said predetermined device type laterally adjacent said conductive structure;

said first control element having a cross-sectional area that is larger than a cross-sectional area of said first memory storage element;

a second memory storage element of said predetermined device type and a second control element of said predetermined device type laterally adjacent said conductive structure; and

said second control element having a cross-sectional area that is larger than a cross-sectional area of said second memory storage element.

30. The memory structure of claim 29 further including:

further conductive structure having a vertical extent vertically adjacent said conductive pillar;

a third memory storage element of said predetermined device type and a third control element of said predetermined device type laterally adjacent said further conductive structure;

said third control element having a cross-sectional area that is larger than a cross-sectional area of said third memory storage element;

a fourth memory storage element of said predetermined device type and a fourth control element of said predetermined device type laterally adjacent said further conductive structure; and

said fourth control element having a cross-sectional area that is larger than a cross-sectional area of said fourth memory storage element.

31. A memory structure comprising:

means of a predetermined device type for storing a memory state;

means of said predetermined device type for controlling said means for storing;

said means for storing having a smaller cross-sectional area than said means for controlling.

32. A memory structure comprising:

a first conductive tub having a base and a rim that are vertically separated;

a first memory selection conductor vertically adjacent said base of said first conductive tub;

a first control element of disposed between said first memory selection conductor and said base of said first conductive tub;

a second memory selection conductor vertically adjacent a portion of said rim of said first conductive tub;

a first memory storage element disposed between said rim of said first conductive tub and said second memory selection conductor;

said first control element having a cross-sectional area that is larger than a cross-sectional area of said first memory storage element;

a second conductive tub having a base and a rim that are vertically separated, said base being vertically adjacent said second memory selection conductor;

a second control element disposed between said second memory selection conductor and said base of said second conductive tub;

a third memory selection conductor vertically adjacent a portion of said rim of said second conductive tub;

a second memory storage element disposed between a portion of said rim of said second conductive tub and said third memory selection conductor;

said second control element having a cross-sectional area that is larger than a cross-sectional area of said second memory storage element.

33. The memory structure of claim 32 wherein said first conductive tub and said second conductive tub are horizontally offset.

34. A memory structure comprising:

a plurality of layers of memory cells;

each memory cell comprising a first electrode, a second electrode, a third electrode, a memory storage element disposed between said second electrode and said third electrode, and a control element disposed between said first electrode and said second electrode; and

said control element having a cross-sectional area that is greater than a cross-sectional area of said memory storage element.

35. The memory structure of claim 34 wherein:

said second electrode comprises a conductive tub having a base and a rim that are vertically separated;

said first electrode comprises a first memory selection conductor vertically adjacent said base of said conductive tub;

said control element is disposed between said first memory selection conductor and said base of said conductive tub;

said third electrode comprises a second memory selection conductor vertically adjacent a portion of said rim of said conductive tub; and

said memory storage element is disposed between said second memory selection conductor and said rim of said conductive tub.

36. The memory structure of claim 34 wherein:

said third electrode comprises a conductive pillar;

said second electrode comprises a conductor laterally adjacent said conductive pillar; and

said memory storage element is disposed between said conductive pillar and said conductor.

37. The memory structure of claim 34 wherein:

said third electrode comprises a conductive tub;

said second electrode comprises a conductor laterally adjacent said conductive tub; and

said memory storage element is disposed between said conductive tub and said conductor.

38. A memory structure comprising:

a plurality of layers of memory cells;

each memory cell comprising means for storing a memory state and means for controlling said means for storing; and

said means for storing having a smaller cross-sectional area than said means for controlling.

39. A method of making a memory structure comprising:

creating a first electrode;

forming on the first electrode a control element of a predetermined device type on the first electrode;

creating a second electrode; and

forming a memory storage element of the predetermined device type and having a cross-sectional area that is smaller than a cross-sectional area of the control element.

40. The method of claim 39 wherein forming the control element on the first electrode comprises forming an oxide different from an oxide of the first electrode.

41. The method of claim 39 wherein forming the memory storage element on the second electrode comprises forming an oxide different from an oxide of the second electrode.

42. The method of claim 39 wherein:

forming the memory storage element comprises forming the memory storage element on a top surface of the first electrode;

forming the control element comprises forming the control element on a top surface of the second electrode.

43. The method of claim 39 wherein:

forming the control element comprises forming the control element on a side surface of the first electrode;

creating a second electrode comprises creating a second electrode that is in contact with the control element and laterally adjacent the first electrode;

forming the memory storage element comprises forming the memory storage element on a side surface of the second electrode.

44. The method of claim 39 further including forming a conductive structure having vertical extent in contact with the memory storage element and laterally adjacent the second electrode.

45. The method of claim 39 wherein:

forming the control element comprises forming the control element on a horizontal surface of the first electrode;

creating a second electrode comprises forming a conductive tub vertically adjacent the first electrode and having a base in contact with the control element and a rim vertically separated from the base; and

forming the memory storage element comprises forming the memory storage element on the rim of the conductive tub.

46. A memory structure made in accordance with the method of claim 39.

47. A method of making a memory structure comprising:

forming in a first memory layer a plurality of memory cells each including a memory storage element and a control storage element having a cross-sectional area that is larger than a cross-sectional area of the memory storage element; and

forming in a second memory layer a plurality of memory cells each including a memory storage element and a control storage element having a cross-sectional area that is larger than a cross-sectional area of the memory storage element.

48. The method of claim 47 wherein forming in a first memory layer a plurality of memory cells comprises forming in the first memory layer a plurality of memory tunnel junction oxide regions and a plurality of control tunnel junction oxide regions.

49. A memory structure made in accordance with the method of claim 47.