Dual damascene barrier structures and preferential etching method

• US 20030190829A1
• Filed: 04/05/2002
• Published: 10/09/2003
• Est. Priority Date: 04/05/2002
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Brennan, Kenneth D.
• Application Number:
  US10/117,486
• Publication Number:
  US 20030190829A1
• Time in Patent Office: Days
• US Class Current: 439/200
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multilevel metal interconnect structure and method of fabrication for semiconductor integrated circuits. A first horizontal metal interconnector line, for example copper, is topped by a stack of horizontal insulating layers alternating between etch stop and dielectric layers so that the bottom etch stop layer is selected to be etchable at a first rate by a selected etchant, while the upper etch stop layers are selected to be etchable at a second rate by the same selected etchant. Preferably, the first etch rate is about ten times faster than the second etch rate. When a vertical trench and via are etched into the stack, the bottom stop layer can be opened for contact to the first metal line without etching the other stop layers substantially. Trench and via are finally filled with metal, for instance copper, to form the second level interconnector line and the via contact to the first level metal line.

Claims

1. A multilevel metal interconnect structure for semiconductor integrated circuits, comprising:

a first level horizontal metal interconnector lines, on an insulated semiconductor substrate;

a first horizontal insulating layer over said metal line, said first insulating layer operable as first etch stop and selected to be etchable at a first rate by a selected etchant;

a second insulating layer operable as first circuit dielectric over said first insulator;

a third insulating layer over said second insulator, said third insulating layer operable as second etch stop and selected to be etchable at a second rate by said selected etchant;

a fourth insulating layer operable as second circuit dielectric over said third insulator;

a fifth insulating layer over said fourth insulator, said fifth insulating layer operable as third etch stop and selected to be etchable at said second rate by said selected etchant;

a trench approximately vertically oriented through said third etch stop and said second dielectric;

a via approximately vertically oriented and aligned with said trench, through said first dielectric and said first etch stop; and

said trench and said via filled with metal so that said metal in said trench forms the second level interconnector line, and said metal in said via contacts said first level metal line.

2. The structure according to claim 1 wherein said metal and metal lines are copper.

3. The structure according to claim 1 wherein said first insulating layer is made of silicon carbon nitride, silicon nitride, any other nitride-containing silicon compound, or silicon carbon oxide in the thickness range from 50 to 75 nm.

4. The structure according to claim 1 wherein said second and fourth dielectric layer are porous low-k dielectric materials in the thickness range from 250 to 500 nm.

5. The structure according to claim 1 wherein said third and fifth insulating layers are made of silicon carbide in the thickness range from 30 to 50 nm.

6. The structure according to claim 1 further comprising a sixth insulating layer topping said fifth insulating layer, said sixth insulating layer made of silicon carbo nitride or silicon nitride in the thickness range from 50 to 150 nm. Alternatively, the fifth insulating layer, made of silicon carbide, may have a thickness range from 50 to 100 nm.

7. A method of fabricating integrated circuit multi-level interconnects comprising horizontal trenches and vertical vias between metal lines, comprising the steps of:

forming first horizontal metal interconnector lines on an insulated semiconductor substrate;

depositing the bottom first stop layer over said first metal lines, said first stop layer selected to be etchable at a first rate by a selected etchant;

depositing the first dielectric layer over said bottom first stop layer;

depositing the second stop layer over said first dielectric layer, said second stop layer selected to be etchable at a second rate by said selected etchant;

depositing the second dielectric layer over said second stop layer;

depositing the third stop layer over said second dielectric layer, said third stop layer selected to be etchable at said second rate by said selected etchant said third stop layer being the top layer;

depositing a first photoresist layer over said third stop layer;

patterning said photoresist layer to create a plurality of holes, each hole having the dimensions defining said vias;

using said selected etchant, etching into said third stop layer, at said second etch rate, for a period of time sufficient to remove all of said third stop layer and said second dielectric layer, thereby defining said vias in said second dielectric layer;

stripping said first photoresist layer;

depositing a second photoresist layer over the remainder of said third stop layer;

patterning said photoresist layer to create a plurality of openings nested around said defined vias and having the outline of each of said trenches;

using said selected etchant, etching into said third stop layer, at said second etch rate, for a period of time sufficient to remove all of said third stop layer and said second dielectric layer, thereby defining said trenches in said second dielectric layer, while concurrently continuing to etch said via completely through said second stop layer and said first dielectric layer;

continuing using said selected etchant, etching said via into said first stop layer, at said first etch rate, for a period of time sufficient to remove all of said first stop layer, thereby exposing said first metal line in said via, while said second and third stop layers are barely etched; and

filling said trench and said via with metal, thereby forming in the trench the second horizontal metal interconnector line and contact, by the via, the first metal.

8. The method according to claim 7 wherein said metal is copper.

9. The method according to claim 7 wherein said first stop layer is made of silicon carbon nitride, silicon nitride, any other nitride-containing silicon compound, or silicon carbon oxide in the thickness range from 50 to 75 nm.

10. The method according to claim 7 wherein said first and second dielectric layers are porous low-k dielectric materials in the thickness range from 300 to 500 nm.

11. The method according to claim 7 wherein said second and third stop layer are silicon carbide in the thickness range from 30 to 50 nm.

12. The method according to claim 7 wherein said selected etchant comprises:

a gas mixture of controlled amounts of a saturated carbon hydride halogen constituent, an inert constituent, and an oxidizing constituent; and

a plasma initiated in said gas mixture under an RF power reduced compared to standard plasma conditions.

13. The method according to claim 12 wherein said saturated carbon hydride halogen constituent is a gaseous compound selected from a group consisting of a first portion as methyl, ethyl, propyl, and butyl, and a second portion as fluorine, chlorine, bromine, and iodine.

14. The method according to claim 13 wherein the amount of said saturated carbon hydride halogen constituent in said gas mixture is preferably 40 parts.

15. The method according to claim 12 wherein said saturated carbon hydride halogen constituent is CH3F (methyl fluoride, fluorocarbon).

16. The method according to claim 12 wherein said saturated carbon hydride halogen is C2H2F or CHF3.

17. The method according to claim 12 wherein said inert constituent is selected from a group consisting of nitrogen, helium, neon, argon, krypton, and xenon.

18. The method according to claim 17 wherein the amount of said inert constituent in said gas mixture is preferably 100 parts.

19. The method according to claim 12 wherein said oxidizing constituent is selected from a group consisting of oxygen and fluorine.

20. The method according to claim 19 wherein the amount of said oxidizing constituent in said gas mixture is preferably between 10 and 20 parts.

21. The method according to claim 12 wherein said reduced RE power is between 200 and 300 W, representing a 25 to 50% reduction compared to standard plasma conditions.

22. The method according to claim 12 wherein said first etch rate is approximately 150 nm/min.

23. The structure according to claim 12 wherein said second etch rate is approximately 15 nm/min.