Multi-way select instructions using accumulated condition codes
First Claim
1. A method for providing a multi-way select instruction in a processor, the method comprising:
- decoding an instruction as a multi-way select instruction;
selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers;
selecting a final source operand from each of said selected at least one pair of source operands; and
outputting each of said selected final source operands.
1 Assignment
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Accused Products
Abstract
The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.
5 Citations
41 Claims
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1. A method for providing a multi-way select instruction in a processor, the method comprising:
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decoding an instruction as a multi-way select instruction;
selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers;
selecting a final source operand from each of said selected at least one pair of source operands; and
outputting each of said selected final source operands. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A processor, said processor comprising:
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a decoder to decode an instruction as a multi-way select instruction; and
a circuit coupled to said decoder, said circuit in response to said decoded instruction to, select at least two source operands from a plurality of instruction operands using information from a plurality of parallel control registers;
select a final source operand from each of said selected at least two source operands; and
output each of said selected final source operands. - View Dependent Claims (37)
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38. A computer system, said computer system comprising:
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a processor; and
a machine-readable medium coupled to the processor in which is stored one or more instructions adapted to be executed by the processor, the instructions which, when executed, configure the processor to decode an instruction as a multi-way select instruction;
select at least two source operands from a plurality of instruction operands using information from a plurality of parallel control registers;
select a final source operand from each of said selected at least two source operands; and
output each of said selected final source operands. - View Dependent Claims (39)
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40. A machine-readable medium, said machine-readable medium having stored thereon one or more instructions adapted to be executed by a processor, the instructions which, when executed, configure the processor to:
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decode an instruction as a multi-way select instruction;
select at least two source operands from a plurality of instruction operands using information from a plurality of parallel control registers;
select a final source operand from each of said selected at least two source operands; and
output each of said selected final source operands. - View Dependent Claims (41)
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Specification