RF MEMS switch loop 180 degree phase bit radiator circuit

• US 20030193377A1
• Filed: 04/11/2002
• Published: 10/16/2003
• Est. Priority Date: 04/11/2002
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Quan, Clifton, Pierce, Brian M.
• Granted Patent: US 6,674,340 B2
• Time in Patent Office: Days
• US Class Current: 333/164
• CPC Class Codes: H01P 1/127 Strip line switches
• CPC Class Codes: H01P 5/10 for coupling balanced lines or devices with unbalanced lines or devices
• CPC Class Codes: H01Q 3/38 the phase-shifters being digital

Abstract

A switched loop RF radiator circuit, comprising a radiator element, a circuit RF input/output (I/O) port, and a balun coupled between the radiator element and the I/O port. The balun includes a 180° switched loop circuit having two transmission line legs coupled to a balun transition to provide a selectable 180° phase shift, and a microelectromechanically machined (MEM) switch cirtuit. Many radiator circuits can be deployed in an electronically scanned antenna array.

Claims

1. A switched loop RF radiator circuit, comprising:

a radiator element;

a circuit RF input/output (I/O) port;

a balun coupled between the radiator element and the I/O port, the balun including a 180°

switched loop circuit having first and second transmission line legs coupled to a balun transition to provide a selectable 180°

phase shift, and a microelectromechanically machined (MEM) switch circuit to select one of said transmission line legs.

2. The circuit of claim 1, wherein the first and second transmission line legs each have an effective electrical length of one quarter wavelength at an operating signal for the circuit.

3. The circuit of claim 1 wherein the radiator element is a dipole.

4. The circuit of claim 1 wherein the switch circuit includes first and second single-pole-single-throw (SPST) MEM switch circuits.

5. The circuit of claim 4, wherein a first pole of said first MEM switch circuit is connected to a first transmission line, a second pole of said first MEM switch circuit is connected to the first transmission line leg, a first pole of said second MEM switch is connected to a second transmission line, and a second pole of the second MEM switch circuit is connected to the second transmission line leg, the first and second transmission lines connected together at a junction and coupled to the I/O port.

6. The circuit of claim 5, wherein the first and second transmission lines each have an effective electrical length of one half wavelength at an operating frequency.

7. The circuit of claim 5, wherein in a first circuit phase state, the first MEM switch is set to a closed state, and the second MEM switch is set to an open state, and in a second phase state mode the first MEM switch is set to an open state and the second MEM switch is set to a closed state to provide a 180°

phase difference from the first phase state.

8. The circuit of claim 7, wherein in a reflective state, the first and second MEM switches are both set to the closed state to reflect incident RF energy.

9. The circuit of claim 2 wherein the switch circuit includes a single-pole-double-throw (SPDT) MEM switch circuit.

10. The circuit of claim 9, wherein a first pole of said SPDT MEM switch circuit is connected to the first transmission line leg, a second pole of the SPDT MEM switch circuit is connected to the second transmission line leg, and a third pole of the SPDT switch circuit is coupled to the I/O port.

11. The circuit of claim 10, wherein said SPDT MEM switch circuit has first, second and third switch states, said first state wherein said first pole is connected to said third pole and said second pole is isolated from said third pole, said second state wherein said second pole is connected to said third pole and said first pole is isolated from said third pole, and said third state wherein both said first pole and said second pole are isolated from the third pole.

12. The circuit of claim 1, further including:

a primary transmission line coupled between the MEM switch circuit and the RF I/O port;

a secondary transmission line coupled between the MEM switch circuit and a secondary RF I/O port;

the MEM switch circuit includes a first SPDT MEM switch circuit connected between said first transmission line leg, said primary transmission line and said secondary transmission line, and a second SPDT MEM switch circuit connected between said second transmission line leg, said primary transmission line and said secondary transmission line;

wherein the first SPDT switch circuit selectively connects the first transmission line leg to the primary transmission line or to the secondary transmission line, the first SPDT switch circuit further having an open circuit state, and the second SPDT switch circuit selectively connects the second transmission line leg to the primary transmission line or to a matched load termination, the second SPDT switch circuit further having an open circuit state.

13. The circuit of claim 1, wherein said MEM switch circuit comprises MEM metal-metal contact switches.

14. The circuit of claim 13, wherein said radiator element, said balun and said MEM switch circuit are all fabricated on a common dielectric substrate.

15. An electronically scanned array, comprising:

a linear array of radiator circuits, each circuit including a radiator element, a circuit RF input/output (I/O) port, a balun coupled between the radiator element and the I/O port, the balun including a 180°

switched loop circuit having two transmission line legs coupled to a balun transition to provide a selectable 180°

phase shift, and a microelectromechanically machined (MEM) switch circuit to select one of said transmission line legs;

an array of phase shifters coupled to the I/O ports of the radiator circuits;

an RF manifold including a plurality of phase shifter ports respectively coupled to a corresponding phase shifter RF port and an RF port; and

an array controller for providing control signals to the phase shifters to control the phase shift setting of the array of the phase shifters and to the MEM switch circuits.

16. The array of claim 15, wherein said MEM switch circuit comprises MEM metal-metal contact switches.

17. The array of claim 16, wherein, for each radiator circuit, said radiator element, said balun and said MEM switch circuit are all fabricated on a common dielectric substrate.

18. The array of claim 15 wherein, for each radiator circuit, the switch circuit includes first and second single-pole-single-throw (SPST) MEM switch circuits, and wherein a first pole of said first MEM switch circuit is connected to a first transmission line, a second pole of said first MEM switch circuit is connected to the first transmission line leg, a first pole of said second MEM switch is connected to a second transmission line, and a second pole of the second MEM switch circuit is connected to the second transmission line leg, the first and second transmission lines connected together at a junction and coupled to the I/O port.

19. The array of claim 18, wherein in a first array phase state, for each radiator circuit, the first MEM switch is set to a closed state, and the second MEM switch is set to an open state, and in a second phase state mode the first MEM switch is set to an open state and the second MEM switch is set to a closed state to provide a 180°

phase difference from the first phase state.

20. The array of claim 19, wherein in a reflective state, the first and second MEM switches of each radiator circuit are both set to the closed state to reflect incident RF energy.

21. The array of claim 15 wherein, for each radiator circuit, the switch circuit includes a single-pole-double-throw (SPDT) MEM switch circuit, and wherein a first pole of said SPDT MEM switch circuit is connected to the first transmission line leg, a second pole of the SPDT MEM switch circuit is connected to the second transmission line leg, and a third pole of the SPDT switch circuit is coupled to the I/O port.

22. The array of claim 20, wherein said SPDT MEM switch circuit has first, second and third switch states, said first state wherein said first pole is connected to said third pole and said second pole is isolated from said third pole, said second state wherein said second pole is connected to said third pole and said first pole is isolated from said third pole, and said third state wherein both said first pole and said second pole are isolated from the third pole.

23. The array of claim 15, further including, for each radiator circuit:

a primary transmission line coupled between the MEM switch circuit and the RF I/O port;

a secondary transmission line coupled between the MEM switch circuit and a secondary RF I/O port;

the MEM switch circuit includes a first SPDT MEM switch circuit connected between said firsttransmission line leg, said primary transmission line and said secondary transmission line, and a second SPDT MEM switch circuit connected between said second transmission line leg, said primary transmission line and said secondary transmission line;

wherein the first SPDT switch circuit selectively connects the first transmission line leg to the primary transmission line or to the secondary transmission line, the first SPDT switch circuit further having an open circuit state, and the second SPDT switch circuit selectively connects the second transmission line leg to the primary transmission line or to a matched load termination, the second SPDT switch circuit further having an open circuit state.