Image sensor with processor controlled integration time

• US 20030193594A1
• Filed: 03/06/2003
• Published: 10/16/2003
• Est. Priority Date: 04/16/2002
• Status: Abandoned Application

• Current Assignee: Candela Microsystems Incorporated
• Original Assignee: Candela Microsystems Incorporated
• Inventors: Tay, Hiok Nam
• Application Number:
  US10/383,450
• Publication Number:
  US 20030193594A1
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/42 by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling

Abstract

An image sensor that has one or more pixels within a pixel array. The pixels are arranged within a plurality of rows within the array. Each row of the pixel array can be selected by a row decoder in response to an edge of a control signal. The control signal may be one of a plurality of signals generated by a processor coupled to the image sensor. The processor can control the exposure time of the pixels by varying the control signals. The control signals may also have an embedded narrow pulse that is used to determine the location of a “window” in the pixel array.

Claims

1. An image sensor that is connected to a processor which generates a plurality of control signals, the control signals including a first edge separated from a second edge by a control interval, comprising:

a pixel array that contains a plurality of rows of pixels; and

,

a selection circuit that selects a row of said pixel array to generate and retrieve pixel data from said pixel array by resetting and reading said selected row of said pixel array, a time interval between the resetting and reading of said selected row being proportional to the control interval between the first and second edges.

2. The image sensor of claim 1, wherein said selection circuit includes a decoder circuit coupled to said pixel array, an address generator coupled to said decoder circuit and a pulse detector coupled to said address generator and the processor.

3. The image sensor of claim 2, wherein said address generator circuit includes a first counter that is started in response to the first edge and a second counter that is started in response to the second edge.

4. The image sensor of claim 3, wherein said selection circuit includes a narrow pulse detector that is coupled to a third counter of said address generator, said third counter being coupled to said decoder circuit.

5. The image sensor of claim 3, wherein said decoder circuit includes a multiplexor coupled to an address decoder, said multiplexor being coupled to said first and second counters.

6. The image sensor of claim 5, wherein said selection circuit includes a row driver coupled to a latch of said decoder circuit, said latch being coupled to said address decoder.

7. The image sensor of claim 1, further comprising a light reader circuit coupled to said pixel array.

8. The image sensor of claim 4, wherein said selection circuit includes a counter/latch that is coupled to said narrow pulse detector and said address generator.

9. The image sensor of claim 6, wherein said selection circuit includes a phase sequence decoder that is coupled to said light reader circuit and said row driver.

10. An image sensor that is connected to a processor which generates a plurality of control signals including a first pulse that has a first width and a second pulse that has a different second width, comprising:

a pixel array that contains a plurality of rows of pixels; and

,

a selection circuit that selects a group of rows of said pixel array, the group being a function of a location of the second pulse relative to the first pulse.

11. The image sensor of claim 10, wherein said selection circuit includes a decoder circuit coupled to said pixel array, an address generator coupled to said decoder circuit and a pulse detector coupled to said address generator and the processor.

12. The image sensor of claim 11, wherein said address generator includes a first counter that is started in response to a first edge in the plurality of control signals and a second counter that is started in response to a second edge in the plurality of control signals selection.

13. The image sensor of claim 12, wherein said logic circuit includes a pulse detector that is coupled to a third counter of said address generator, said third counter being coupled to said decoder circuit.

14. The image sensor of claim 12, wherein said decoder circuit includes a multiplexor coupled to an address decoder, said multiplexor being coupled to said first and second counters.

15. The image sensor of claim 14, wherein said selection circuit includes a row driver coupled to a latch of said decoder circuit, said latch being coupled to said address decoder.

16. The image sensor of claim 10, further comprising a light reader circuit coupled to said pixel array.

17. The image sensor of claim 13, wherein said selection circuit includes a counter/latch that is coupled to said pulse detector and said address generator.

18. The image sensor of claim 16, wherein said selection circuit includes a phase sequence decoder that is coupled to said light reader circuit and said row driver.

19. An image sensor, comprising:

a pixel array that contains a plurality of rows of pixels;

an address decoder coupled to a row of said pixel array;

a multiplexor coupled to said address decoder;

a first address generator coupled to said multiplexor; and

,

a second address generator coupled to said multiplexor.

20. The system of claim 19, further comprising a pulse detector coupled to said first and second address generators.