Image sensor with time overlapping image output

• US 20030193699A1
• Filed: 05/23/2003
• Published: 10/16/2003
• Est. Priority Date: 11/06/2001
• Status: Active Grant

• Current Assignee: Candela Microsystems Incorporated
• Original Assignee: Candela Microsystems Incorporated
• Inventors: Tay, Hiok Nam
• Granted Patent: US 8,054,357 B2
• Time in Patent Office: Days
• US Class Current: 358/474
• CPC Class Codes: H04N 1/32358 using picture signal storage, e.g. at transmitter H04N1/17 takes precedence
• CPC Class Codes: H04N 1/32475 Changing the format of the data, e.g. parallel to serial or vice versa
• CPC Class Codes: H04N 1/32491 alternate storage in and retrieval from two parallel memories, e.g. using ping-pong buffers
• CPC Class Codes: H04N 1/40 Picture signal circuits H04N1/387 takes precedence
• CPC Class Codes: H04N 2201/0081 Image reader H04N2201/0091 - H04N2201/0094 take precedence
• CPC Class Codes: H04N 2201/3292 of one or two complete lines
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/447 by preserving the colour pattern with or without loss of information
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor
• CPC Class Codes: H04N 9/64 Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84
• CPC Class Codes: H04N 9/642 Multi-standard receivers

Abstract

An image sensor system with an image sensor that generates a first image and a second image. The first and second images are transmitted to a processor in a time overlapping manner. By way of example, the images may be transferred to the processor in an interleaving manner or provided on separate dedicated busses.

Claims

1. An image sensor system, comprising:

an image sensor that generates a first image and a second image, said image sensor transmits the first image and the second image in a time overlapping manner; and

,

a processor coupled to said image sensor and receives the first and second images in the time overlapping manner.

2. The system of claim 1, further comprising a memory device coupled to said processor.

3. The system of claim 1, further comprising a non-volatile memory device coupled to said processor, said non-volatile memory device including a program that causes said processor to receive the first and second images in the time overlapping manner.

4. The system of claim 2, wherein said processor contains a DMA controller to transfer the first and second images to said memory device.

5. The system of claim 1, further comprising a first bus that couples said image sensor to said processor.

6. The system of claim 5, further comprising a second bus that couples said image sensor to said processor, the first image is transmitted across said first bus and the second image is transmitted across said second bus.

7. The system of claim 5, wherein the first and second images are transmitted to said processor in an interleaving manner.

8. The system of claim 2, further comprising a first bus that couples said memory device to said image sensor.

9. An image sensor system, comprising:

image sensor means for generating and transmitting a first image and a second image in a time overlapping manner; and

,

processor means for receiving the first and second images in the time overlapping manner and processing the first and second images.

10. The system of claim 9, further comprising memory means for storing the first and second images.

11. The system of claim 9, further comprising non-volatile memory means for storing a program that causes said processor means to receive the first and second images in the time overlapping manner.

12. The system of claim 10, wherein said processor means contain a DMA controller to transfer the first and second images to said memory means.

13. The system of claim 9, further comprising a first bus that couples said image sensor means to said processor means.

14. The system of claim 13, further comprising a second bus that couples said image sensor means to said processor means, the first image is transmitted across said first bus and the second image is transmitted across said second bus.

15. The system of claim 13, wherein the first and second images are received by said processor means in an interleaving manner.

16. The system of claim 10, further comprising a first bus that couples said memory means to said image sensor means.

17. A method for transferring a first image and a second image, comprising:

generating a first image from a pixel array of an image sensor;

generating a second image from the pixel array;

transferring the first and second images from the image sensor to a processor in a time overlapping manner;

transferring at least the first image to a memory device.

18. The method of claim 17, wherein the first and second images are transferred in an interleaving manner.

19. A processor that is coupled to an image sensor that transmits a first image and a second image, comprising:

a processor that receives the first image and the second image in a time overlapping manner.

20. The processor of claim 19, wherein said processor has a memory bus coupled to an external memory.

21. The processor of claim 19, wherein said processor operates in accordance with a program that causes said processor to receive the first and second images in the time overlapping manner.

22. The processor of claim 20, wherein said processor contains a DMA controller to transfer the first and second images to the external memory in a time overlapping manner.

23. The processor of claim 19, wherein said processor includes a first bus that is coupled the image sensor.

24. The processor of claim 23, wherein said processor includes a second bus that is coupled the image sensor, the first image is transmitted across said first bus and the second image is transmitted across said second bus.

25. The processor of claim 23, wherein said processor receives the first and second images in an interleaving manner.

26. A processor that is coupled to an image sensor that transmits a first image and a second image, comprising:

processor means for receiving the first image and the second image in a time overlapping manner.

27. The processor of claim 26, wherein said processor means has a memory bus coupled to an external memory.

28. The processor of claim 26, wherein said processor means operates in accordance with a program that causes said processor to receive the first and second images in the time overlapping manner.

29. The processor of claim 27, wherein said processor means contains a DMA controller to transfer the first and second images to the external memory in a time overlapping manner.

30. The processor of claim 26, wherein said processor means includes a first bus that is coupled the image sensor.

31. The processor of claim 30, wherein said processor means includes a second bus that is coupled the image sensor, the first image is transmitted across said first bus and the second image is transmitted across said second bus.

32. The processor of claim 30, wherein said processor receives the first and second images in an interleaving manner.

33. A computer program storage medium that can cause a processor to receive a first image and a second image from an image sensor, comprising:

a computer readable storage medium that contains a program which causes a processor to receive a first image and a second image from an image sensor in a time overlapping manner.

34. The storage medium of claim 33, wherein said program causes the processor to receive the first and second images in an interleaving manner.