Method, apparatus, and system for maintaining conflict-free memory address space for input/output memory subsystems
First Claim
1. A method comprising:
- programming a first address translation unit in a first input/output (I/O) processor for a minimum amount of memory addresses required to accept control transactions on a first bus;
programming a second address translation unit in the first I/O processor to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;
in response to an incoming host request being received from a host, determining whether the host request'"'"'s reply address overlaps with the memory address range for the second address translation unit; and
if the host request'"'"'s reply address overlaps with the memory address range, dynamically changing a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via the local memory of the first I/O processor.
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Abstract
According to one embodiment of the present invention, an apparatus is provided which includes a first address translation unit and a second address translation unit. The first address translation unit is programmed for a minimum amount of memory addresses required to accept control transactions on a first bus. The second address translation unit is programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory space required by the I/O interconnect device. The apparatus includes logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit. The apparatus further includes logic to dynamically alter a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to host via the local memory of the first I/O processor, if the reply address overlaps with the memory address range for the second address translation unit.
10 Citations
29 Claims
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1. A method comprising:
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programming a first address translation unit in a first input/output (I/O) processor for a minimum amount of memory addresses required to accept control transactions on a first bus;
programming a second address translation unit in the first I/O processor to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;
in response to an incoming host request being received from a host, determining whether the host request'"'"'s reply address overlaps with the memory address range for the second address translation unit; and
if the host request'"'"'s reply address overlaps with the memory address range, dynamically changing a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to the host via the local memory of the first I/O processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An apparatus comprising:
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a first address translation unit programmed for a minimum amount of memory addresses required to accept control transactions on a first bus;
a second address translation unit programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;
logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit; and
logic to dynamically alter a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to host via the local memory of the first I/O processor, if the reply address overlaps with the memory address range for the second address translation unit. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A system comprising:
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a host processor coupled to transmit data to and receive data from one or more input/output (I/O) devices; and
an input/output (I/O) processor coupled to the host processor via a host bus to manage input/output operations with respect to the one or more I/O devices, the I/O processor including;
a first address translation unit programmed for a minimum amount of memory addresses required to accept control transactions on a first bus;
a second address translation unit programmed to a memory address range that corresponds to an amount of local memory for caching operations between the I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;
logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit; and
logic to dynamically alter a data flow between the first I/O interconnect device and the host processor such that data from the first I/O interconnect device is transferred to host processor via the local memory of the I/O processor, if the reply address overlaps with the memory address range for the second address translation unit. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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Specification