Semiconductor device and method of manufacturing the same

• US 20030201494A1
• Filed: 10/02/2002
• Published: 10/30/2003
• Est. Priority Date: 04/25/2002
• Status: Active Grant

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Maeda, Shigenobu, Matsumoto, Takuji, Iwamatsu, Toshiaki, Ipposhi, Takashi
• Granted Patent: US 7,005,705 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Claims

1. A semiconductor device comprising:

an MOS transistor provided on an SOI layer of an SOI substrate in which a semiconductor substrate, a buried insulating film and said SOI layer are sequentially provided; and

a body contact portion provided in a surface of said SOI layer and capable of fixing an electric potential from an outside,

a gate electrode of said MOS transistor having a shape seen on a plane such that at least one of ends in a direction of a gate width is enlarged in a direction of a gate length to constitute a gate contact pad,

said body contact portion being provided in said surface of said SOI layer on an outside of said end in said direction of said gate width of said gate contact pad and being electrically connected to a channel formation region provided under said gate electrode through said SOI layer,

a gate insulating film of said MOS transistor including a first portion having a first thickness and a second portion having a second thickness in said direction of said gate width, and

said second thickness being greater than said first thickness,

wherein said second portion of said gate insulating film is provided at least under said gate contact pad.

2. The semiconductor device according to claim 1, wherein an insulating film having said second thickness including said second portion of said gate insulating film is provided under said gate contact pad and therearound.

3. The semiconductor device according to claim 2, wherein said insulating film having said second thickness is provided on said SOI layer to be a connecting portion of said body contact portion and said channel formation region.

4. The semiconductor device according to claim 3, wherein a length in a direction of a gate length of said SOI layer to be said connecting portion of said body contact portion and said channel formation region is smaller than a length obtained by adding a gate length of said gate electrode and a double of a width of a side wall insulating film provided on a side surface of said gate electrode.

5. The semiconductor device according to claim 2, wherein a length in said direction of said gate length of said SOI layer to be said connecting portion of said body contact portion and said channel formation region is smaller than a length in said direction of said gate length of said gate contact pad.

6. A semiconductor device comprising:

an MOS transistor provided on an SOI layer of an SOI substrate in which a semiconductor substrate, a buried insulating film and said SOI layer are sequentially provided; and

a body contact portion provided in a surface of said SOI layer and capable of fixing an electric potential from an outside,

a gate insulating film of said MOS transistor including a first portion having a first thickness and a second portion having a second thickness in a direction of a gate width, and

said second thickness being greater than said first thickness,

wherein said body contact portion is provided like a band adjacently to a source region of said MOS transistor in said surface of said SOI layer on an outside of an edge portion in said direction of said gate width in said source region, and

an insulating film having said second thickness including said second portion of said gate insulating film is provided on one of two ends in said direction of said gate width of a gate electrode of said MOS transistor in which said band-shaped body contact portion is provided.