Dynamic electrically alterable programmable read only memory device

• US 20030205754A1
• Filed: 06/11/2003
• Published: 11/06/2003
• Est. Priority Date: 07/29/1997
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Geusic, Joseph E.
• Granted Patent: US 7,242,049 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Claims

1. A memory cell comprising:

a storage electrode for storing charge; and

an insulator adjacent to the storage electrode, wherein a barrier energy between the insulator and the storage electrode is less than approximately 3.3 eV.

2. The memory cell of claim 1, wherein materials comprising at least one of the storage electrode and the insulator are selected to have an electron affinity causing the barrier energy to be selected at less than approximately 3.3 eV.

3. The memory cell of claim 2, wherein the barrier energy is selected to obtain a desired data charge retention time of less than or equal to approximately 40 seconds at 250 degrees Celsius.

4. The memory cell of claim 2, wherein the barrier energy is selected to obtain a desired erase time of less than approximately 1 second.

5. The memory cell of claim 2, wherein the barrier energy is selected to obtain a desired erase voltage of less than approximately 12 Volts.

6. The memory cell of claim 1, wherein the insulator comprises a material that has a material composition that is selected to obtain a larger electron affinity than silicon dioxide.

7. The memory cell of claim 1, wherein the storage electrode comprises a material that has a material composition that is selected to obtain a smaller electron affinity than polycrystalline silicon.

8. The memory cell of claim 1, wherein the barrier energy is less than approximately 2.0 eV.

9. The memory cell of claim 1, wherein the storage electrode is isolated from conductors and semiconductors.

10. The memory cell of claim 1, wherein the storage electrode is transconductively capacitively coupled to a channel.

11. A transistor comprising:

a source region;

a drain region;

a channel region between the source and drain regions; and

a floating gate separated from the channel region by an insulator, wherein a barrier energy between the floating gate and the insulator is less than approximately 3.3 eV.

12. The transistor of claim 11, wherein materials comprising at least one of the floating gate and the insulator are selected to have an electron affinity causing the barrier energy to be selected at less than approximately 3.3 eV.

13. The transistor of claim 12, wherein the barrier energy is selected to obtain a data charge retention time of the transistor that is adapted for dynamic refreshing of charge stored on the floating gate.

14. The transistor of claim 11, wherein the floating gate is isolated from conductors and semiconductors.

15. The transistor of claim 11, wherein the insulator comprises a material that has a material composition that is selected to obtain a larger electron affinity than silicon dioxide.

16. The transistor of claim 11, wherein the floating gate includes a material that has a material composition that is selected to obtain a smaller electron affinity than polycrystalline silicon.

17. The transistor of claim 11, further comprising a control electrode, separated from the floating gate by an intergate dielectric.

18. The transistor of claim 17, wherein the area of a capacitor formed by the control electrode, the floating gate, and the intergate dielectric is larger than the area of a capacitor formed by the floating gate, the insulator, and the channel region.

19. The transistor of claim 17, wherein the intergate insulator has a permittivity that is higher than a permittivity of silicon dioxide.

20. The transistor of claim 11, wherein the floating gate is capacitively separated from the channel region for providing transconductance gain.

21. A method of using a floating gate transistor having a barrier energy of less than approximately 3.3 eV at an interface between a floating gate electrode and an adjacent insulator, the method comprising:

storing data by changing the charge of the floating gate;

reading data by detecting a current between a source and a drain; and

refreshing data based on a data charge retention time that depends upon the barrier energy.

22. The method of claim 21, wherein storing data by changing the charge of the floating gate transconductively provides an amplified signal between the source and the drain.

23. The method of claim 21, wherein the detected current is based on the charge of the floating gate and a transconductance gain of the floating gate transistor.

24. A method of forming a floating gate transistor, the method comprising:

forming source and drain regions;

selecting floating gate and gate insulator materials such that a barrier energy at an interface therebetween is less than approximately 3.3 eV;

forming a gate insulator from the gate insulator material; and

forming a floating gate from the gate material, such that the floating gate is isolated from conductors and semiconductors.

25. The method of claim 24, wherein selecting the floating gate and gate insulator materials is based on a desired data charge retention time of less than or equal to approximately 40 seconds at 250 degrees Celsius.

26. The method of claim 25, wherein the data charge retention time is based on refreshing charge stored on the floating gate.

27. A memory device comprising:

a plurality of memory cells, wherein each memory cell includes a transistor comprising;

a source region;

a drain region;

a channel region between the source and drain regions;

a floating gate separated from the channel region by an insulator, wherein an interfacial barrier energy between the floating gate and the insulator is less than approximately 3.3 eV; and

a control gate located adjacent to the floating gate and separated therefrom by an intergate dielectric.

28. A memory cell comprising:

a storage electrode comprising a material that has an electron affinity less than 4.2 eV to store charge;

an insulator adjacent to the storage electrode, wherein a barrier energy between the insulator and the storage electrode is less than approximately 3.3 eV; and

a control electrode separated from the storage electrode by an intergate dielectric.

29. The memory cell of claim 28, wherein materials comprising at least one of the storage electrode and the insulator are selected to have an electron affinity causing the barrier energy to be selected at less than approximately 3.3 eV.

30. The memory cell of claim 29, wherein the barrier energy is selected to obtain a desired data charge retention time of less than or equal to approximately 40 seconds at 250 degrees Celsius.

31. The memory cell of claim 29, wherein the barrier energy is selected to obtain a desired erase time of less than approximately 1 second.

32. The memory cell of claim 29, wherein the barrier energy is selected to obtain a desired erase voltage of less than approximately 12 Volts.

33. The memory cell of claim 28, wherein the insulator comprises a material that has a material composition that is selected to obtain an electron affinity greater than 0.9 eV.

34. The memory cell of claim 28, wherein the barrier energy is less than approximately 2.0 eV.

35. The memory cell of claim 28, wherein the storage electrode is isolated from conductors and semiconductors.

36. The memory cell of claim 28, wherein the storage electrode is transconductively capacitively coupled to a channel.

37. The memory cell of claim 28, further comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region; and

wherein;

the storage electrode comprises polycrystalline or microcrystalline silicon carbide;

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator is between the storage electrode and the channel region, the insulator comprising a material that has a larger electron affinity than silicon dioxide, and the barrier energy is less than approximately 2.0 eV; and

an area of a capacitor formed by the control electrode, the storage electrode, and the intergate dielectric is larger than an area of a capacitor formed by the storage electrode, the insulator, and the channel region.

38. A transistor comprising:

a source region;

a drain region;

a channel region between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control electrode separated from the floating gate by an intergate dielectric.

39. The transistor of claim 38, wherein materials comprising at least one of the floating gate and the insulator are selected to have an electron affinity causing the barrier energy to be selected at less than approximately 3.3 eV.

40. The transistor of claim 39, wherein the barrier energy is selected to obtain a data charge retention time of the transistor that is adapted for dynamic refreshing of charge stored on the floating gate.

41. The transistor of claim 38, wherein the floating gate is isolated from conductors and semiconductors.

42. The transistor of claim 38, wherein the insulator comprises a material that has a material composition that is selected to obtain an electron affinity greater than 0.9 eV.

43. The transistor of claim 38, wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the barrier energy is less than approximately 2.0 eV; and

an area of a capacitor formed by the control electrode, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

44. The transistor of claim 38, wherein the floating gate is capacitively separated from the channel region for providing transconductance gain.

45. A transistor comprising:

a source region;

a drain region;

a channel region between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 2.0 eV;

a control electrode separated from the floating gate by an intergate dielectric.

46. The transistor of claim 45 wherein:

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide; and

an area of a capacitor formed by the control electrode, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

47. A memory device comprising:

a plurality of memory cells, wherein each memory cell includes a transistor comprising;

a source region;

a drain region;

a channel region between the source and drain regions;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate located adjacent to the floating gate and separated therefrom by an intergate dielectric.

48. The memory device of claim 47 wherein materials comprising at least one of the floating gate and the insulator in each transistor are selected to have an electron affinity causing the barrier energy to be less than approximately 3.3 eV.

49. The memory device of claim 48 wherein the barrier energy is selected to obtain a data charge retention time for each transistor that is adapted for dynamic refreshing of charge stored on the floating gate.

50. The memory device of claim 47 wherein the floating gate of each transistor is isolated from conductors and semiconductors.

51. The memory device of claim 47 wherein the insulator in each transistor comprises a material that has an electron affinity greater than 0.9 eV.

52. The memory device of claim 47 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the barrier energy is less than approximately 2.0 eV; and

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region of each transistor.

53. The memory device of claim 47 wherein the floating gate of each transistor is capacitively separated from the channel region for providing transconductance gain.

54. The memory device of claim 47, further comprising:

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.

55. A transistor comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

an insulator comprising a material that has an electron affinity greater than 0.9 eV;

a floating gate separated from the channel region by the insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

56. The transistor of claim 55 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises amorphous silicon carbide;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the barrier energy is less than approximately 2.0 eV.

57. A transistor comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

58. The transistor of claim 57 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the barrier energy is less than approximately 2.0 eV.

59. A transistor comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV;

a control gate separated from the floating gate by an intergate dielectric; and

wherein an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

60. The transistor of claim 59 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV; and

the barrier energy is less than approximately 2.0 eV.

61. A transistor comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

an insulator comprising a material that has an electron affinity greater than 0.9 eV;

a floating gate separated from the channel region by the insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV;

a control gate separated from the floating gate by an intergate dielectric; and

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

62. The transistor of claim 61 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises amorphous silicon carbide;

the barrier energy is less than approximately 2.0 eV; and

the floating gate comprises polycrystalline or microcrystalline silicon carbide.

63. A transistor comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

64. The transistor of claim 63 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the barrier energy is less than approximately 2.0 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV; and

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

65. A transistor comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 2.0 eV;

a control gate separated from the floating gate by an intergate dielectric; and

wherein an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

66. The transistor of claim 65 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV; and

the floating gate comprises polycrystalline or microcrystalline silicon carbide.

67. A memory cell comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

an insulator comprising a material that has an electron affinity greater than 0.9 eV;

a floating gate separated from the channel region by the insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

68. The memory cell of claim 67 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises amorphous silicon carbide;

the barrier energy is less than approximately 2.0 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide; and

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

69. A memory cell comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

70. The memory cell of claim 69 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the barrier energy is less than approximately 2.0 eV;

the insulator comprises a material that has an electron affinity greater than 0.9 eV; and

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

71. A memory cell comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV;

a control gate separated from the floating gate by an intergate dielectric; and

wherein an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

72. The memory cell of claim 71 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the barrier energy is less than approximately 2.0 eV;

the insulator comprises a material that has an electron affinity greater than 0.9 eV; and

the floating gate comprises polycrystalline or microcrystalline silicon carbide.

73. A memory cell comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 2.0 eV; and

a control gate separated from the floating gate by an intergate dielectric.

74. The memory cell of claim 73 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide; and

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

75. A memory device comprising:

a plurality of memory cells, each memory cell comprising;

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

an insulator comprising a material that has an electron affinity greater than 0.9 eV;

a floating gate separated from the channel region by the insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

76. The memory device of claim 75 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the insulator comprises amorphous silicon carbide;

the barrier energy is less than approximately 2.0 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the memory device further comprises;

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.

77. A memory device comprising:

a plurality of memory cells, each memory cell comprising;

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

78. The memory device of claim 77 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the barrier energy is less than approximately 2.0 eV;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the memory device further comprises;

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.

79. A memory device comprising:

a plurality of memory cells, each memory cell comprising;

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 2.0 eV; and

a control gate separated from the floating gate by an intergate dielectric.

80. The memory device of claim 79 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the memory device further comprises;

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.

81. A memory device comprising:

a plurality of memory cells, each memory cell comprising;

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV;

a control gate separated from the floating gate by an intergate dielectric; and

wherein an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region.

82. The memory device of claim 81 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the barrier energy is less than approximately 2.0 eV;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV; and

the memory device further comprises;

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.

83. A memory cell comprising:

a storage electrode to store charge, the storage electrode comprising a material that has an electron affinity less than 4.2 eV;

an insulator adjacent to the storage electrode, wherein a barrier energy between the insulator and the storage electrode is less than approximately 3.3 eV; and

a control electrode separated from the storage electrode by an intergate dielectric.

84. The memory cell of claim 83, further comprising:

a source region in a substrate;

a drain region in the substrate;

a channel region in the substrate between the source region and the drain region; and

wherein the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

wherein the insulator is between the storage electrode and the channel region, the insulator comprising a material that has an electron affinity greater than 0.9 eV; and

wherein an area of a capacitor formed by the control electrode, the storage electrode, and the intergate dielectric is larger than an area of a capacitor formed by the storage electrode, the insulator, and the channel region.

85. A memory device comprising:

a plurality of memory cells, wherein each memory cell includes a transistor comprising;

a source region;

a drain region;

a channel region between the source and drain regions;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV; and

a control gate separated from the floating gate by an intergate dielectric.

86. The memory device of claim 85 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the insulator comprises a material that has an electron affinity greater than 0.9 eV;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the memory device further comprises;

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.

87. A memory device comprising:

a plurality of memory cells, wherein each memory cell includes a transistor comprising;

a source region;

a drain region;

a channel region between the source and drain regions;

a floating gate separated from the channel region by an insulator, the floating gate comprising a material that has an electron affinity less than 4.2 eV and a barrier energy between the floating gate and the insulator being less than approximately 3.3 eV, the floating gate being capacitively separated from the channel region to provide transconductance gain; and

a control gate separated from the floating gate by an intergate dielectric.

88. The memory device of claim 87 wherein:

the intergate dielectric has a permittivity that is higher than a permittivity of silicon dioxide;

the floating gate comprises polycrystalline or microcrystalline silicon carbide;

the barrier energy is less than approximately 2.0 eV;

the insulator comprises a material that has a larger electron affinity than silicon dioxide;

an area of a capacitor formed by the control gate, the floating gate, and the intergate dielectric is larger than an area of a capacitor formed by the floating gate, the insulator, and the channel region; and

the memory device further comprises;

a row decoder;

a column decoder;

a command and control circuit;

a voltage control circuit; and

wherein the memory cells are arranged in an array.