High performance silicon contact for flip chip

• US 20030207566A1
• Filed: 04/17/2003
• Published: 11/06/2003
• Est. Priority Date: 02/08/2001
• Status: Active Grant

• Current Assignee: Kie Y. Ahn, Leonard Forbes
• Original Assignee: Kie Y. Ahn, Leonard Forbes
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 6,828,656 B2
• Time in Patent Office: Days
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/10252 Germanium [Ge]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10271 Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1432 Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1435 Random access memory [RAM]
• CPC Class Codes: H01L 2924/145 Read-only memory [ROM]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/09036 : Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 2201/09809 : Coaxial layout reduction of cross-talk, noise or interference by printed shielding conductors for shielding around a single via or around a group of vias H05K1/0222
• CPC Class Codes: H05K 2201/09845 : Stepped hole, via, edge, bump or conductor

Abstract

The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.

Claims

1. A method of forming coaxial integrated circuitry interconnect lines comprising:

providing a substrate having front and back surfaces;

forming a hole with sidewalls extending through said substrate from said front to said back surface;

forming an outer conductive coaxial sheath on said sidewalls;

forming a coaxial dielectric layer radially inward and over said outer conductive coaxial sheath; and

forming an inner coaxial fine radially inward and over said coaxial dielectric layer.

2. The method of claim 1 wherein said act of forming an inner coaxial line further comprises the act of:

forming an inner conductive layer;

forming a seed layer over said inner conductive layer; and

electroplating a metal on said seed layer.

3. The method of claim 1 wherein said conductive sheath is a tungsten sheath.

4. The method of claim 3 wherein said conductive sheath is formed by low pressure chemical vapor deposition.

5. The method of claim 4 wherein said deposition is performed at a rate of about 1 micron per minute.

6. The method of claim 1 wherein said sheath is formed to a to thickness of about 0.3 μ

m to about 0.5 μ

m.

7. The method of claim 1 wherein said dielectric layer comprises silicon dioxide.

8. The method of claim 1 wherein said dielectric layer is formed to a thickness of about 0.5 μ

m to about 0.8 μ

m.

9. The method of claim 1 wherein said dielectric layer comprises a nitride containing layer.

10. The method of claim 9 wherein said nitride containing layer is formed by low pressure chemical vapor deposition.

11. The method of claim 2 wherein said inner conductive layer is a polysilicon layer.

12. The method of claim 2 wherein said seed layer is formed to a thickness of about 20 nm-40 nm.

13. The method of claim 2 wherein said metal is copper.

14. The method of claim 2 wherein said electroplated layer is about 2-3 μ

m thick.

15. The method of claim 1 further comprising the act of fabricating circuit devices on said substrate.

16. The method of claim 1 further comprising the act of mounting integrated circuit chips on said substrate.

17. The method of claim 16 further comprising the act of encapsulating said integrated circuit chip and substrate.

18. An integrated circuitry interconnect line comprising:

a substrate having front and back surfaces;

a hole with sidewalls extending through said substrate from said front to said back surface;

an outer conductive coaxial sheath formed on said sidewalls;

a coaxial dielectric layer formed radially inward and over said outer coaxial line; and

a conductive inner coaxial line formed radially inward and over said coaxial dielectric layer.

19. The interconnect line of claim 18 wherein said inner conductive coaxial line further comprises:

an inner conductive layer;

a seed layer provided over said inner conductive layer; and

a electroplated metal layer on said seed layer.

20. The interconnect line of claim 18 wherein said conductive sheath comprises a tungsten layer.

21. The interconnect line of claim 18 wherein said sheath is formed to a thickness of about 0.3 μ

m to about 0.5 μ

m.

22. The interconnect line of claim 18 wherein said dielectric layer comprises silicon dioxide.

23. The interconnect line of claim 18 wherein said dielectric layer is formed to a thickness of about 0.5 μ

m to about 0.8 μ

m.

24. The interconnect line of claim 18 wherein said dielectric layer comprises a nitride containing layer.

25. The interconnect line of claim 18 wherein said dielectric to layer comprises silicon nitride.

26. The interconnect line of claim 19 wherein said inner conductive layer is a polysilicon layer.

27. The interconnect line of claim 19 wherein said seed layer is formed to a thickness of about 20 nm-40 nm.

28. The interconnect line of claim 19 wherein said metal is copper.

29. The interconnect line of claim 19 wherein said electroplated layer is about 2-3 μ

m thick.

30. A processor system comprising:

a processor; and

an integrated circuit coupled to said processor, at least one of said integrated circuit and processor comprising;

a substrate having front and back surfaces and a hole with sidewalls extending through said substrate from said front to said back surface;

a conductive outer coaxial sheath formed on said sidewalls;

a coaxial dielectric layer formed radially inward and over said outer coaxial sheath; and

a inner conductive coaxial line formed radially inward and over said coaxial dielectric layer.

31. The system of claim 30 wherein said inner coaxial line further comprises:

an inner conductive layer;

a seed layer provided over said inner conductive layer; and

a electroplated metal layer on said seed layer.

32. The system of claim 30 wherein said conductive sheath is a tungsten sheath.

33. The system of claim 30 wherein said sheath is formed to a thickness of about 0.3 μ

m to about 0.5 μ

m.

34. The system of claim 30 wherein said dielectric layer comprises silicon dioxide.

35. The system of claim 30 wherein said dielectric layer is formed to a thickness of about 0.5 μ

m to about 0.8 μ

m.

36. The system of claim 30 wherein said dielectric layer comprises a nitride containing layer.

37. The system of claim 30 wherein said dielectric layer comprises silicon nitride.

38. The system of claim 31 wherein said inner conductive layer, is a polysilicon layer.

39. The system of claim 31 wherein said seed layer is formed to a thickness of about 20 nm-40 nm.

40. The system of claim 31 wherein said metal is copper.

41. The system of claim 31 wherein said electroplated layer is about 2-3 μ

m thick.

42. A integrated circuit package comprising:

a substrate supporting at least one integrated circuit chip, said substrate having front and back surfaces and at least a hole with sidewalls extending through said substrate from said front to said back surface;

an outer conductive coaxial sheath formed on said sidewalls;

a coaxial dielectric layer formed radially inward and over said outer conductive coaxial sheath; and

an inner conductive coaxial line formed radially inward and over said coaxial dielectric layer; and

a package which encases said substrate and said at least one chip.

43. The integrated circuit of claim 42 wherein said inner coaxial line further comprises:

an inner conductive layer;

a seed layer provided over said inner conductive layer; and

a electroplated metal layer on said seed layer.

44. The integrated circuit of claim 42 wherein said conductive sheath is a tungsten sheath.

45. The integrated circuit of claim 42 wherein said sheath is formed to a thickness of about 0.3 μ

m to about 0.5 μ

m.

46. The integrated circuit of claim 42 wherein said dielectric layer comprises silicon dioxide.

47. The integrated circuit of claim 42 wherein said dielectric layer is formed to a thickness of about 0.5 μ

m to about 0.8 μ

m.

48. The integrated circuit of claim 42 wherein said dielectric layer comprises a nitride containing layer.

49. The integrated circuit of claim 42 wherein said dielectric layer comprises silicon nitride.

50. The integrated circuit of claim 43 wherein said inner conductive layer is a polysilicon layer.

51. The integrated circuit of claim 43 wherein said seed layer is formed to a thickness of about 20 nm-40 nm.

52. The integrated circuit of claim 43 wherein said metal is copper.

53. The integrated circuit of claim 43 wherein said electroplated layer is about 2-3 μ

m thick.