Non-volatile semiconductor memory device and data programming method

• US 20030210571A1
• Filed: 04/16/2003
• Published: 11/13/2003
• Est. Priority Date: 08/27/1993
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwahashi, Hiroshi
• Granted Patent: US 6,785,166 B2
• Time in Patent Office: Days
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltage thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

Claims

1. A non-volatile semiconductor memory device, comprising:

a memory cell array including memory cells arranged in a matrix form having rows and columns, each of the memory cells having a drain, a source, a floating gate and a control gate, and having a threshold voltage varying in dependence upon an amount of charges of the floating gate;

row lines, to each of which the control gates of the memory cells in the same row are commonly connected;

column lines, to each of which the drains of the memory cells in the same column are commonly connected;

a row decoder for selecting at least one of the row lines;

data detecting means for detecting data stored in the memory cell;

data writing means for writing data to the memory cell by injecting electrons to the floating gate of the memory cell; and

data erasing means for erasing data of the memory cell, wherein the data erasing means emits the electrons from the floating gate of the memory cell, and then the electrons are injected to the floating gate of the memory cell;

wherein a programming voltage is applied to the control gate of the memory cell in order to inject electrons to the floating gate of the memory cell, and the value of said programming voltage at the time of the injection of electrons performed by said data writing means is higher than the value of said programming voltage at the time of the injection of electrons performed by said data erasing means.