Fuse for use in a semiconductor device, and semiconductor devices including the fuse

• US 20030211661A1
• Filed: 04/21/2003
• Published: 11/13/2003
• Est. Priority Date: 04/16/1999
• Status: Active Grant

• Current Assignee: Kenneth W. Marr, Michael P. Violette
• Original Assignee: Kenneth W. Marr, Michael P. Violette
• Inventors: Violette, Michael P., Marr, Kenneth W.
• Granted Patent: US 6,979,601 B2
• Time in Patent Office: Days
• US Class Current: 438/128
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Claims

1. A method for fabricating a fuse of a semiconductor device, comprising:

imparting first regions of a semiconductor substrate with a first conductivity type;

imparting second regions of said semiconductor substrate with a second conductivity type, each second region of said second regions being located adjacent to or at least partially surrounded by a corresponding first region of said first regions following said imparting said first regions and said imparting said second regions;

forming a layer comprising metal silicide over said first regions and said second regions; and

forming the fuse from said layer, including at least two terminal regions that are each positioned adjacent to a corresponding one of said first and second regions and a narrowed region between said at least two terminal regions and located over a boundary between said first and second regions.

2. The method of claim 1, wherein said imparting said first regions with said first conductivity type comprises imparting said first regions with an n-type conductivity.

3. The method of claim 1, wherein said imparting said second regions comprises imparting said second regions with a p-type conductivity.

4. The method of claim 1, wherein said forming said layer comprises depositing said metal silicide.

5. The method of claim 4, wherein said depositing comprises chemical vapor depositing said metal silicide.

6. The method of claim 1, wherein said forming said layer comprises forming a layer comprising metal adjacent an active surface of said semiconductor substrate and annealing said metal to silicon or polysilicon adjacent said layer comprising metal.

7. The method of claim 6, further comprising forming another layer comprising silicon or polysilicon adjacent said layer comprising metal.

8. The method of claim 7, wherein said annealing comprises annealing said metal to at least said silicon or polysilicon of said another layer.

9. The method of claim 1, wherein said forming the fuse comprises forming a mask over said layer comprising metal silicide and removing selected regions of said layer comprising metal silicide through said mask.

10. The method of claim 9, wherein said removing comprises etching said selected regions of said layer comprising metal silicide.

11. The method of claim 6, wherein said forming the fuse comprises forming a mask over said layer comprising metal and removing selected regions of said layer through said mask prior to said annealing.

12. The method of claim 11, wherein said removing comprises etching said selected regions through said mask.

13. The method of claim 1, further comprising:

forming a contact in communication with each of said at least two terminal regions of the fuse.

14. The method of claim 1, wherein said imparting second regions comprises imparting at least two spaced-apart second regions of said semiconductor substrate with said second conductivity type, each of said at least two second regions being located adjacent to or at least partially surrounded by said first region.

15. A method for fabricating a fuse of a semiconductor device, comprising:

forming at least one first well of a first conductivity type in a semiconductor substrate, adjacent to a surface thereof;

forming at least one second well of a second conductivity type within or laterally adjacent to said first well and adjacent to said surface; and

forming at least one fusible element including a fusible region on said surface, said fusible region overlapping a boundary between said at least one first well and said at least one second well.

16. The method of claim 15, wherein said forming said at least one first well comprises imparting at least a first region of said semiconductor substrate with said first conductivity type.

17. The method of claim 16, wherein said forming said at least one first well comprises doping said at least one first region to have said first conductivity type.

18. The method of claim 15, wherein said forming said at least one first well comprises forming said at least one first well to have an n-type conductivity.

19. The method of claim 15, wherein said forming said at least one second well comprises imparting at least one second region of said semiconductor substrate with said second conductivity type.

20. The method of claim 19, wherein said forming said at least one second well comprises doping said at least one second region to have said second conductivity type.

21. The method of claim 15, wherein said forming said at least one second well comprises forming said at least one second well to have a p-type conductivity.

22. The method of claim 15, wherein said forming said at least one fusible element comprises:

forming a layer comprising metal silicide adjacent said surface.

23. The method of claim 22, wherein said forming said at least one fusible element further comprises:

patterning said layer comprising metal silicide to form said fusible region.

24. The method of claim 22, wherein said forming said layer comprises depositing metal silicide onto at least a portion of said surface.

25. The method of claim 24, wherein said depositing comprises chemical vapor depositing said metal silicide.

26. The method of claim 22, wherein said forming said layer comprises:

forming a layer comprising metal over at least a portion of said surface; and

annealing said metal to adjacent silicon, polysilicon, metal silicide, or polycide.

27. The method of claim 26, further comprising:

forming another layer comprising semiconductive material adjacent to said layer comprising metal.

28. The method of claim 27, wherein said forming said another layer comprises forming said another layer between said surface and said layer comprising metal.

29. The method of claim 27, wherein said forming said another layer comprises forming said another layer on said layer comprising metal.

30. The method of claim 27, wherein said annealing comprises annealing said metal to said semiconductive material of said another layer.

31. The method of claim 26, wherein said annealing comprises annealing said metal to semiconductive material of said semiconductor substrate.

32. The method of claim 15, further comprising:

forming a contact in communication with a terminal of said at least one fusible element and said at least one second well.

33. The method of claim 32, further comprising:

forming another contact to communicate with another terminal of said at least one fusible element and said at least one first well.

34. The method of claim 15, wherein said forming said at least one second well comprises forming at least two second wells, each second well of said at least two second wells being located adjacent to or at least partially surrounded by said at least one first well.