Systems and methods providing scan-based delay test generation

• US 20030212970A1
• Filed: 05/13/2002
• Published: 11/13/2003
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Stong, Gayvin E.
• Granted Patent: US 6,769,101 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G01R 31/318328 for delay tests
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

Chip analyzer systems and methods are provided to partition chip designs into smaller blocks in order to test speed paths more efficiently for integrated circuits. In accordance with one aspect of the invention, a system includes a chip analyzer and an automatic test generator. The chip analyzer partitions information corresponding to the integrated circuit into a plurality of circuit configuration blocks, and creates a model of a selected circuit configuration block in the integrated circuit. The automatic test generator receives the model from the chip analyzer, and creates tests from the model to determine the correctness of the integrated circuit. In accordance with another aspect of the invention, the method partitions the integrated circuit into a plurality of circuit configurations, and selects a circuit configuration on the integrated circuit to be tested. Then, the method identifies logic driving input logic in the selected circuit configuration of the integrated circuit; and identifies logic driving output logic in the selected circuit configuration of the integrated circuit.

Claims

1. A method for testing speed paths for an integrated circuit comprising the steps of:

partitioning the integrated circuit into a plurality of circuit configurations;

selecting a circuit configuration on the integrated circuit to be tested;

identifying logic driving input logic in the selected circuit configuration of the integrated circuit; and

identifying logic driving output logic in the selected circuit configuration of the integrated circuit.

2. The method as defined in claim 1, further comprising:

including the identified logic in a generated test program.

3. The method as defined in claim 1, wherein the step of identifying logic driving input logic in the selected circuit configuration further comprises:

identifying all second level registers driving the input logic in the selected circuit configuration for inclusion in the test program.

4. The method as defined in claim 3, wherein the step of identifying logic driving input logic in the selected circuit configuration further comprises:

identifying all logic outside the selected circuit configuration driving all the second level registers for inclusion in the test program.

5. The method as defined in claim 4, wherein the step of identifying logic driving input logic in the selected circuit configuration further comprises:

identifying all first level registers driving the logic outside the selected circuit configuration for inclusion in the test program.

6. The method as defined in claim 1, wherein the step of identifying logic driving output logic further comprises:

identifying all second level registers driving the output logic in the selected circuit configuration for inclusion in the test program.

7. The method as defined in claim 6, wherein the step of identifying logic driving output logic in the selected circuit configuration further comprises:

identifying all logic outside the selected circuit configuration driving all the second level registers for inclusion in the test program.

8. The method as defined in claim 7, wherein the step of identifying logic driving output logic in the selected circuit configuration further comprises:

identifying all first level registers driving the logic outside the selected circuit configuration for inclusion in the test program.

9. The method as defined in claim 1, further comprising:

identifying all result registers driven by the selected circuit configuration for inclusion in the test program.

10. A system for testing speed paths for an integrated circuit comprising:

means for partitioning the integrated circuit into a plurality of circuit configurations;

means for selecting a circuit configuration on the integrated circuit to be tested;

means for identifying logic driving input logic in the selected circuit configuration of the integrated circuit; and

means for identifying logic driving output logic in the selected circuit configuration of the integrated circuit.

11. The system of claim 10, wherein the selecting means further comprises:

means for including the identified logic in a generated test program.

12. The system of claim 10, further comprising:

means for identifying all second level registers driving the input logic in the selected circuit configuration for inclusion in the test program.

13. The system of claim 12, further comprising:

means for identifying all logic outside the selected circuit configuration driving all the second level registers for inclusion in the test program.

14. The system of claim 13, further comprising:

means for identifying all first level registers driving the logic outside the selected circuit configuration for inclusion in the test program.

15. The system of claim 10, further comprising:

means for identifying all second level registers driving the output logic in the selected circuit configuration for inclusion in the test program.

16. The system of claim 15, further comprising:

means for identifying all logic outside the selected circuit configuration driving all the second level registers for inclusion in the test program.

17. The system of claim 16, further comprising:

means for identifying all first level registers driving the logic outside the selected circuit configuration for inclusion in the test program.

18. The system of claim 10, further comprising:

means for identifying all result registers driven by the selected circuit configuration for inclusion in the test program.

19. A computer readable storage medium containing program code for testing speed paths for an integrated circuit comprising:

a first code segment configured to partition the integrated circuit into a plurality of circuit configurations;

a second code segment configured to select a circuit configuration on the integrated circuit to be tested;

a third code segment configured to identify logic driving input logic in the selected circuit configuration of the integrated circuit; and

a fourth code segment configured to identify logic driving output logic in the selected circuit configuration of the integrated circuit.

20. The program code of claim 19, further comprising:

a fifth code segment configured to include the identified logic in a generated test program.

21. The program code of claim 19, wherein said third code segment is further configured to identify all second level registers driving the input logic the selected circuit configuration for inclusion in the test program.

22. The program code of claim 21, wherein said third code segment is further configured to identify all logic outside the selected circuit configuration driving all the second level registers for inclusion in the test program.

23. The program code of claim 22, wherein said third code segment is further configured to identify all first level registers driving the logic outside the selected circuit configuration for inclusion in the test program.

24. The program code of claim 19, wherein said fourth code segment is further configured to identify all second level registers driving the output logic in the selected circuit configuration for inclusion in the test program.

25. The program code of claim 24, wherein said fourth code segment is further configured to identify all logic outside the selected circuit configuration driving all the second level registers for inclusion in the test program.

26. The program code of claim 25, wherein said fourth code segment is further configured to identify all first level registers driving the logic outside the selected circuit configuration for inclusion in the test program.

27. The program code of claim 19, further comprising:

a sixth code segment configured to identify all result registers driven by the selected circuit configuration for inclusion in the test program.

28. A system for testing speed paths for an integrated circuit comprising:

a chip analyzer that partitions information corresponding to the integrated circuit into a plurality of circuit configuration blocks, and creates a model of a selected circuit configuration block in the integrated circuit; and

an automatic test generator that receives the model from the chip analyzer, and creates tests from the model to determine the correctness of the integrated circuit.

29. The system of claim 28, wherein the chip analyzer further comprises:

input analysis driving logic configured to identify logic driving input circuits in the selected circuit configuration block of the integrated circuit.

30. The system of claim 29, input analysis driving logic further comprises:

logic configured to identify all second level registers driving the input logic in the selected circuit configuration block for inclusion in the test program;

logic configured to identify all circuits outside the selected circuit configuration block driving all the second level registers for inclusion in the test program; and

logic configured to identify all first level registers driving the logic outside the selected circuit configuration block for inclusion in the test program.

31. The system of claim 28, wherein the chip analyzer further comprises:

output analysis driving logic configured to identify circuits driving output circuits in the selected circuit configuration block of the integrated circuit.

32. The system of claim 31, output analysis driving logic further comprises:

logic configured to identify all second level registers driving the output circuits in the selected circuit configuration block for inclusion in the test program;

logic configured to identify all circuits outside the selected circuit configuration block driving all the second level registers for inclusion in the test program; and

logic configured to identify all first level registers driving the circuits outside the selected circuit configuration block for inclusion in the test program.

33. The system of claim 30, further comprising:

logic configured to identify all result registers driven by the selected circuit configuration block for inclusion in the test program.