Highly compact Eprom and flash EEprom devices
First Claim
1. A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
- forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate, forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface, forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions, removing said spacer, and forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed.
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Accused Products
Abstract
Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
224 Citations
149 Claims
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1. A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate, forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface, forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions, removing said spacer, and forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of forming a split-channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer, forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate a second channel region between the source region and the opposite floating gate side, forming a control gate extending over at least a portion of the floating gate and said second channel region, said control gate being electrically insulated from said floating gate and said substrate, forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and forming a pair of parallel erase gates extending between the source and drain regions and across the opposite ends of the floating gate on the tunnel dielectric layers. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method of forming a split-channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer, forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate a second channel region between the source region and the opposite floating gate side, forming a region of a tunnel erase dielectric layer on a portion of the surface of said floating gate, forming an erase gate extending across the floating gate on the tunnel dielectric layer and across the second channel region of the substrate with a dielectric layer therebetween, and forming over and around the erase gate a control gate extending across the floating gate and second channel region, said control gate being electrically insulated from said floating gate and said substrate.
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21. A method of forming a split-channel programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming a first layer of dielectric material across said substrate, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given process while said first layer is not, forming over the second layer a masking layer that has at least two spaced apart openings, implanting source and drain regions in said substrate through said spaced apart openings, said masking layer serving to protect from such implant a channel region in said substrate between the source and drain regions, removing exposed portions of said second layer by said given etching process, including removal of said second layer under the masking layer for a predetermined distance across the channel region from one of said spaced apart openings defining a drain region, removing the masking layer, implanting dopant in the channel region adjacent to the drain region by using a remaining portion of the second layer as a mask for one edge of a heavily doped channel region, stripping remaining portions of said first and second layers of dielectric material, growing a thin gate dielectric oxide film over said channel region, forming a floating gate over said heavily doped channel region and extending a distance on either side thereof but remaining spaced apart from the source region, and forming a control gate over the floating gate and a portion of the channel region adjacent the source region that is not covered by the floating gate. - View Dependent Claims (22, 23, 24)
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25. A method of forming a split channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming a first layer of thin silicon dioxide covered by silicon nitride as an oxidation inhibiting mask, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that has at least two spaced apart openings, removing exposed portions of said second layer by said given process, including removal of said second layer under the masking layer by sideway etching for a predetermined distance from each edge of said masking layer at said openings, implanting source and drain regions in said substrate through said spaced apart openings, said masking layer serving to protect from such implant a channel region in said substrate between the source and drain regions, removing said masking layer, forming an isolation oxide layer over said source and drain regions and over any parts of said substrate surface which is not covered by said oxidation inhibiting mask, implanting dopant in the channel region adjacent to the drain region by using the remaining portion of said second layer as a mask for one edge of a heavily doped channel region extending from said drain by said pre-determined distance towards said source but not extending all the way to said source, stripping the remaining part of said second layer and said first layer but not completely removing said isolation oxide layer, forming a thin gate dielectric oxide film over said channel, forming a floating gate over said heavily doped channel region and extending in a first direction a distance on either side thereof but remaining spaced apart from said source region, said floating gate having a finite extent in a second direction orthogonal to said first direction that terminates in opposite ends thereof, forming a control gate over the floating gate and over a portion of the channel region adjacent the source region that is not covered by the floating gate, and forming a pair of erase gates which overlap at least one of the opposite ends of said floating gate and separated therefrom by a tunnel erase dielectric film, said erase gates being formed to be insulated from said control gate and said substrate surface. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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32. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming on said substrate a plurality of rectangularly shaped floating gates in a two dimensional array of symmetrical rows and columns by use of a first photolithography mask, each floating gate being isolated from said substrate by a gate dielectric layer and having opposing end walls separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of another mask to define a channel between the source and drain regions, forming a tunnel erase dielectric layer on the floating gates in regions adjacent their ends, forming a plurality of control gates that each extend over several of the floating gates with insulation therebetween, and forming on said substrate with a second photolithography mask separate from said first mask a plurality of elongated parallel erase gates separated by a second distance and positioned between rows of floating gates with a width sufficient to contact said erase dielectric regions on the floating gates thereof. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40)
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41. A method of forming a two dimensional array of electrically programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming a first layer of dielectric material across said substrate, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that includes a plurality of openings elongated in a first direction and spaced apart in a second direction that is substantially orthogonal to said first direction, said openings being positioned at locations where source and drain regions are desired to be formed, implanting through said openings alternate source and drain regions in said substrate in said first direction thereacross, said masking layer serving to protect from such implant channel regions in said substrate between adjacent ones of the source and drain regions, removing exposed portions of said second layer by said given etching process, including removal of said second layer under the masking layer for a predetermined distance across the channel region from adjacent openings defining a drain region, removing the masking layer, implanting dopant in the channel regions adjacent to the drain regions by using a remaining portion of the second layer as a mask for one edge of a heavily doped channel region, stripping remaining portions of said first and second layers of dielectric material, growing a thin gate dielectric oxide film over said channel region, forming floating gates over said heavily doped channel regions that extend a distance on either side thereof but which remain spaced apart from the source region, and forming a plurality of control gates elongated in said second direction that extend over a plurality of floating gates and adjacent portions of the channel regions adjacent the source regions that are not covered by the floating gate. - View Dependent Claims (42)
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43. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate surface, comprising the steps of:
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forming a first layer of thin silicon dioxide covered by silicon nitride as an oxidation inhibiting mask, forming a second layer of dielectric material over said first layer, said second layer being etchable by a given etching process while said first layer is not, forming over the second layer a masking layer that includes a plurality of openings elongated in a first direction and spaced apart in a second direction that is substantially orthogonal to said first direction, said openings being positioned at locations where elongated source and drain regions are desired to be formed, removing exposed portions of said second layer by said given etching process, including removal of said second layer under the masking layer by sideway etching a predetermined distance from each edge of said masking layer at said openings, implanting through said openings alternate source and drain regions in said substrate elongated in said first direction thereacross, said masking layer serving to protect from such implant channel regions in said substrate between adjacent ones of the source and drain regions, removing said masking layer, forming an isolation oxide layer over said source and drain regions as well as over any parts of said substrate surface which is not covered by said oxidation inhibiting mask, including regions of isolation between adjacent memory cells, implanting dopant in the channel regions adjacent to said drain regions by using the remaining portion of said second layer as a mask for one edge and said isolation oxide layer over said drain as a mask for a second edge of heavily doped channel regions extending from said drain regions by said predetermined distance towards said source regions but not extending all the way to said source regions, stripping the remaining part of said second layer and said first layer but not completely remvoing said isolation oxide layer, forming a thin gate dielectric oxide film over said channel regions, forming a plurality of floating gates is a first conductive layer on said gate dielectric oxide film, each floating gate overlying a corresponding one of said heavily doped channel regions and extending a distance on either side thereof, but not overlying the second channel portion adjacent to the corresponding one of said source regions, forming a second dielectric layer on said first conductive layer and said substrate, forming in a second conductive layer a plurality of control gate strips elongated in said second direction, each control gate strip extending over several of said floating gates and said second channel portions, forming an insulating film over said control gate strips, removing said second dielectric layer in exposed areas between adjacent ones of said control gate strips, forming a tunnel erase dielectric film on the exposed surfaces of said floating gates at their opposing ends that are not covered by said control gate strips, and forming in a third conductive layer a plurality of erase gate strips elongated in said second direction and positioned over said substrate surface inbetween adjacent ones of said control gate strips, in a manner to overlap at least one of opposing ends of each of said floating gates in the row of memory cells positioned inbetween said adjacent pair of erase gate strips.
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44. A method of forming a two dimensional arry of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming on said substrate a plurality of rectangularly shaped floating gates, each floating gate having opposing sides and opposing ends separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of another mask to define a channel between the source and drain regions, placing a tunnel dielectric layer on the floating gates between their opposing sides intermediate of their opposing ends, forming a plurality of elongated erase gates that each extend across several of the floating gates over the tunnel dielectric thereon, said erase gates having a width significantly less than said first distance, and forming a plurality of elongated control gates coextensive with said erase gates and insulated therefrom, a control gate being formed over and around a floating gate and having a width that is significantly greater than that of said erase gate.
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45. A method of forming a two dimensional array of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming on said substrate a plurality of rectangularly shaped floating gates in a two dimensional array of symmetrical rows and columns by use of a first mask, each floating gate being isolated from said substrate by a gate dielectric layer and having opposing ends separated by a first distance, forming source and drain regions in said substrate by using the plurality of floating gates as a portion of a second mask to define a channel between the source and drain regions, wherein each of said channels has a first channel portion adjacent to said drain region and covered by said floating gate and a second channel portion adjacent to said source region, forming a tunnel erase dielectric layer on the surface of said floating gates, forming on said substrate with a third mask a plurality of elongated parallel erase gates separated by a second distance smaller than said first distance and positioned between adjacent rows of floating gates in the direction extending between said source and drain regions, said erase gates having a width sufficient to contact on opposite sides thereof said tunnel erase dielectric layers of the erase gates at said opposing end of the floating gates thereof, replacing said tunnel erase dielectric layer on the surface of said floating gates which is not covered by said erase gates and on the surface of said substrate which is not covered by said floating gate and said erase gate with a second dielectric layer, said second dielectric layer also forming an insulation layer over said erase gates, and forming by a fourth mask a plurality of elongated parallel control gates in between each pair of said erase gates and extending in the same direction as said erase gates such that each control gate extends over several of the floating gates and their adjacent second channel portions, said control gates being insulated by said second dielectric layer from said floating gates, said second channel portion, and said erase gates. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A method of forming a two dimensional array of symmetrical rows and columns of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming on said substrate a gate dielectric layer, forming on said gate dielectric layer with a first mask a plurality of parallel elongated narrow strips in a first conductive layer with their lengths extending in a first direction, forming source and drain regions in elongated strips in said substrate with their lengths extending in said first direction by using said narrow strips as a portion of a second mask to define channels between said source and drain regions, wherein each such channel between a corresponding one of said source and said drain regions has a first channel portion adjacent to said drain region which is covered by a corresponding one of said narrow strips and a second channel portion adjacent to said source region which is not covered by said narrow strip but adjacent thereto, forming a tunnel erase dielectric layer on the surface of said narrow strips, forming with a third mask in a second conductive layer a plurality of parallel strips of narrow elongated erase gates with their lengths extending in a second direction orthogonal to said first direction, thereby to form said erase gates over a first part of the several of said narrow strips with separation therefrom by said tunnel erase dielectric layer and over a first area of said second channel portion with separation therefrom by the combination of said gate dielectric layer and said tunnel erase dielectric, removing said tunnel erase dielectric layer from the exposed surfaces of said narrow strips and said substrate which are not covered by said narrow erase gates, forming a second dielectric layer on said exposed surfaces and on said narrow erase gates, forming with a fourth mask over said second dielectric layer a third conductive layer in the form of a plurality of parallel strips of elongated control gates with their lengths extending in said second direction, said control gate forming step including forming each of said control gate strips coextensive with but insulated from a corresponding one of said strips of narrow erase gates, over and around the erase-gates by having a width substantially greater than the width of their corresponding narrow erase gates, and overlying a second part of several of said narrow strips of said first conductive layer and overlying a second area of said second channel portion, removing said second dielectric layer in exposed areas between adjacent strips of said control gates, removing said narrow strips of said first conductive layer in exposed areas where said second dielectric layer has-been removed, thereby forming said first conductive layer into individual floating gates whose opposing ends are essentially self-aligned with the edges of said strip of control gate, forming an insulation layer to insulate the exposed edges of said floating gates, and forming channel stop isolation regions at the surface of said substrate between adjacent rows of floating gates. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68)
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69. A method of forming a two dimensional array of symmetrical rows and columns of flash electrically erasable and programmable read only memory cells on a semiconductor substrate, comprising the steps of:
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forming on said substrate a gate dielectric layer, forming on said gate dielectric layer by a first mask a plurality of parallel narrow elongated strips in a first conductive layer with their lengths extending in a first direction, forming source and drain regions in said substrate in elongated narrow strips with their lengths extending in said first direction by using said narrow strips as a portion of a second mask to define channels between said source and drain regions, wherein each such channel between a corresponding one of said source and said drain regions has a first channel portion adjacent to said drain region which is covered by a corresponding one of said narrow strips and a second channel portion adjacent to said source region which is not covered by said narrow strip but adjacent thereto, forming a second dielectric layer on said first conductive layer and said substrate, forming with a third mask in a second conductive layer over said second dielectric layer a plurality of parallel strips of elongated control gates having a given width and their lengths extending in a second direction orthogonal to said first direction, thereby to form each control gate extending over several of said narrow strips and said second channel portions, forming an insulating film over said control gate strips, removing said second dielectric layer in exposed areas between adjacent strips of said control gates, removing said narrow strips of said first conductive layer in exposed areas where said second dielectric layer has been removed, thereby forming said first conductive layer into individual floating gates whose opposing ends are essentially self-aligned with the edges of said strips of control gates, forming a tunnel erase dielectric on the exposed vertical sidewalls of said opposing ends of said floating gates, and forming with a fourth mask in a third conductive layer a plurality of parallel strips of erase gates in said second direction and overlying said substrate between adjacent rows of floating gates and having a strip to strip separation less than said given width so as to overlie said tunnel erase dielectric on said opposing ends of said floating gates. - View Dependent Claims (70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
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80. A flash electrically erasable and programmable read only memory cell, comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, a floating gate positioned at least partially over but insulated from said channel region, said floating gate having a predetermined dimension in one direction between opposing edges thereof, a control gate positioned adjacent to but insulated from the floating-gate and the semiconductor substrate, a pair of erase gates spaced apart a distance less than said predetermined dimension and oriented to extend a part way across the floating gate from its said opposing edges, thereby to form regions of overlap between the floating gate and the pair of erase gates, and a tunnel dielectric positioned between said floating gate and said pair of erase gates in the regions of overlap between them.
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81. A flash electrically erasable and programmable read only memory cell, comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, a floating gate positioned at least partially over but insulated from said channel region, said floating gate having a predetermined dimension between opposing edges thereof in a direction perpendicular to a direction between said source and drain regions, a pair of erase gates spaced apart a distance less than said predetermined dimension and oriented to extend a part way across the floating gate from its said opposing edges, thereby to form regions of overlap between the floating gate and the pair of erase gates, a tunnel dielectric positioned between said floating gate and said pair of erase gates in the regions of overlap between them, and a control gate positioned adjacent to but insulated from said pair of erase gates and also overlying said floating gate. - View Dependent Claims (82, 83)
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84. A flash electrically erasable and programmable read only memory cell, comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, a floating gate positioned at least partially over but insulated from said channel region, a control gate positioned over but insulated from the floating gate and the semiconductor substrate, a pair of erase gates positioned on opposite sides of said floating gate and adjacent to sidewalls thereof, and a tunnel dielectric positioned between the sidewalls of each floating gate at its opposing edges and its adjacent erase gate. - View Dependent Claims (85, 86, 87, 88)
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89. A flash electrically erasable and programmable read only memory cell, comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, a floating gate electrically insulated from the substrate and extending over at least a portion of the channel region between the source and drain regions, an erase gate extending over a portion of the floating gate and separated therefrom by a tunnel dielectric, a control gate provided over the floating gate and extending over the erase gate in a manner to bury at least a portion of said erase gate. - View Dependent Claims (90)
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91. A flash electrically erasable and programmable read only memory cell, comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, a floating gate positioned at least partially over but insulated from said channel region, a control gate positioned over but insulated from the floating gate and the semiconductor substrate, a pair of erase gates positioned on opposite sides of said floating gate and extending across said channel, at least one erase gate and the floating gate having capacitive coupling therebetween, and a thin gate dielectric separating each of the erase gates and the channel region of the substrate, thereby to provide electrical isolation of the cell.
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92. A self-aligned split channel Eprom transistor comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, a floating gate formed over but insulated from a first portion of the channel region, a first edge of said floating gate being aligned with and used to define one edge of said drain region adjacent said first edge, and an opposite second edge of said floating gate overlying said channel region being aligned with and used to define one edge of said source region spaced apart from said second floating gate edge, thereby forming a second portion of said channel region which is not covered by said floating gate, and a control gate formed over but insulated from said floating gate and said second portion of said channel region. - View Dependent Claims (93, 94, 95, 96, 97, 98, 99)
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100. A split-channel Eprom transistor, comprising:
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a semiconductor substrate containing a source region and a drain region separated by a channel region, said channel region including first and second adjacent portions extending between said source and drain, a heavily doped substrate portion contained within said second channel portion immediately adjacent said drain, a floating gate formed over but insulated from said second channel portion, said floating gate not extending completely over said first channel portion, and a control gate formed over but insulated from said floating gate and said first channel portion. - View Dependent Claims (101, 102)
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103. A two dimensional array of flash electrically erasable and programmable read only memory cells, comprising:
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a semiconductor substrate containing in a first direction thereacross alternate source and drain regions that are separated by channel regions, said regions being elongated in a second direction across said substrate that is substantially orthogonal to said first direction, a plurality of control and erase gates elongated in said first direction and alternatively provided across the substrate in said second direction, said control and erase gates being insulated from each other and the substrate, a floating gate provided for each cell of the array of cells that extends in said first direction under a control gate and over at least a portion of a channel region to terminate in said second direction outside of said control gate at opposite ends thereof adjacent the erase gates on either side thereof, said floating gate being insulated from said control gate and the substrate, and a tunnel dielectric positioned to separate the floating gate at each end thereof from its adjacent erase gate. - View Dependent Claims (104, 105, 106, 107, 108, 109, 110)
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111. A two dimensional array of flash electrically erasable and programmable read only memory cells, comprising:
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a semiconductor substrate containing in a first direction thereacross alternate source and drain regions that are separated by channel regions, said regions being elongated in a second direction across said substrate that is substantially orthogonal to said first direction, a plurality of separate floating gates arranged in a two-dimensional array, each of said floating gates having a given dimension in said second direction and being positioned substantially over at least a portion of a channel region with a gate dielectric therebetween, and a plurality of substantially parallel erase and control gate structures elongated in said first direction, a length of each such structure extending across at least several of said plurality of floating gates and including;
an erase gate having a width significantly less than said given dimension and separated from the floating gates by a tunnel dielectric therebetween, said erase gate being insulated from the substrate, and a control gate positioned over and surrounding an erase gate in a manner to be proximate to the floating gate on at least one side of the erase gate, the control gate being insulated from the floating gate, erase gate and substrate. - View Dependent Claims (112, 113)
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- 114. An electrically programmable read only memory cell having memory states dictated by the net electronic charge on a floating gate which modulates conductance of a transistor channel, wherein more than two distinct memory states are obtained by providing means for introducing one of more than two given amounts of electronic charge onto said floating gate for indefinite storage until erased, each one of said given amounts corresponding to a different one of said distinct memory states.
- 116. A flash electrically erasable and programmable read only memory cell having memory states dictated by the net electronic charge on a floating gate which modulates conductance of a transistor channel, wherein more than two distinct memory states are obtained by providing means for introducing one of more than two given amounts of electronic charge onto said floating gate for indefinite storage until removed by electronic erase, each one of said given amounts corresponding to a different one of said distinct memory states.
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118. For an array of electrically erasable and programable read only memory cells having means for addressing individual cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, a method of programming a memory state into an addressed cell of the array, comprising the steps of:
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establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of individually detectable states of the cell in excess of two, erasing the cell by lowering its effective threshold voltage to a base level that is lower than the lowest of the plurality of detectable states of the cell by positively increasing the charge on the floating gate, and programing the cell to one of its said plurality of states by adding negative charge to its floating gate until its effective threshold voltage is substantially equal to one of said plurality of effective threshold voltage levels. - View Dependent Claims (119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130)
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131. For an array of electrically erasable and programmable read only memory cells having means for addressing individual cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, first and second memory states corresponding to first and second effective threshold voltages, respectively, a method of programming an addressed cell of the array into the first or second state, comprising the steps of:
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pulsing said addressed cell for a predetermined time and voltage sufficient to alter the charge on its floating gate and change its effective threshold voltage but insufficient to change the effective threshold voltage by more that approximately one-half the difference between the said first and second effective threshold voltages, thereafter reading the current through the addressed cell to determine whether the effective threshold voltage has reached the new desired first or second state, and repeating the pulsing and reading steps until a desired first or second memory state of the addressed cell is detected by the reading step, at which time the programming of the addressed cell is completed.
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132. For an array of a plurality of electrically erasable and programable read only memory cells having means for addressing the cells to program, read and erase their states, each cell having a field effect transistor with a natural threshold voltage that is alterable by controlling a level of charge on a floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, a method of erasing a memory state from an addressed group of cells of the array, comprising the steps of:
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pulsing the addressed cells for a predetermined time and voltage sufficient to alter the threshold voltage but insufficient to completely erase said cells, thereafter reading the current through the addressed cells in order to ascertain their altered threshold levels, and repeating the pulsing and reading steps a plurality of times, each repeat of the pulsing step increasing the voltage an increment above that of the last pulsing step. - View Dependent Claims (133, 134, 135)
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136. In an array of a plurality of electrically erasable and programable read only memory cells wherein each cell includes a split-channel field effect transistor that has in a semiconductor substrate a source and drain separated by a channel region, a floating gate positioned over only a portion of and insulated from the channel region adjacent the drain, and a control gate extending over and insulated from the floating gate and another portion of the channel adjacent the source, said transistor having a first portion with a natural threshold voltage that is alterable by controlling a level of charge on the floating gate to obtain an effective threshold voltage, wherein said natural threshold voltage corresponds to that when the floating gate has a level of charge equal to zero, the conductance of said first transistor portion being determined by a voltage on the control gate and the level of charge on the floating gate, and said transistor having a second portion in series with said first portion that has a conductance determined by a voltage on said control gate, a system for erasing, programming and reading the memory state of the cells in said array, comprising:
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means operably connected to said array for addressing a selected one or group of the plurality of memory cells, erasing means operably connected to said array for lowering the effective threshold voltage of an addressed cell or group of cells to a base level by positively increasing the charge on each cell'"'"'s floating gate, programming means operably connected to said array for adding negative charge to the floating gate of an addressed cell until its effective threshold voltage is substantially equal to one of a plurality of effective threshold voltage levels in excess of two, whereby each cell of the array is programmable into one of a corresponding number of states in excess of two, and reading means operably connected to said array for determining the amount of current that flows in an addressed cell, wherein a number of individually detectable current levels correspond to the number of effectice threshold voltage levels, whereby the state of an addressed cell is determined from its measured current level. - View Dependent Claims (137, 138, 139)
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140. In an electrically erasable and programmable read only memory system, comprising:
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a semiconductor substrate including an array of a plurality of storage cells in rows and columns, each cell containing a transistor that includes;
a source region and a drain region with a channel therebetween, a floating gate whose level of charge affects the level of conductance between the source and drain, a control gate whose electrical potential affects the level of conductance between the source and drain, column means connectable to an addressed column of said storage cell transisors for controlling a voltage applied to the source and drain regions of the cells therein, row means connectable to an addressed row of said storage cell transistors for controlling the potential level of the control gates of the cells therein, programming means responsive to an address of a particular cell for causing the column means and row means to apply voltages to the addressed cell to increase the electron charge on its floating gate, thereby to decrease the conductance of the addressed cell transistor, reading means responsive to said column means impressing a voltage across the source and drain connections of an addressed column and to the row means increasing the potential level of the control gates of an addressed row for detecting the level of current flow between the source and drain of an addressed cell, thereby determining its state, and erasing means connected with the storage cells of the array for removing electrical charge from the floating gates of a plurality of storage cell transistors, the improvement comprising;
said reading means including means for discriminating between a plurality of more than two current ranges of the addressed cell, each cell thereby having a corresponding plurality of states more than two, and said programming means including means responsive to said reading means for causing said column means and said row means to apply programming voltages to an addressed cell to increase the electron charge on its floating gate until the read current flowing in the addressed cell is within one of the more than two current ranges. - View Dependent Claims (141, 142, 143, 144, 145, 146, 147, 148, 149)
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Specification