Frame memory manager and method for a display system

• US 20030222880A1
• Filed: 05/30/2002
• Published: 12/04/2003
• Est. Priority Date: 05/24/2002
• Status: Abandoned Application

• Current Assignee: Three-Five Systems, Inc.
• Original Assignee: Three-Five Systems, Inc.
• Inventors: Waterman, John Karl
• Application Number:
  US10/158,479
• Publication Number:
  US 20030222880A1
• Time in Patent Office: Days
• US Class Current: 345/531
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 2005/745 Control circuits therefor
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Abstract

A memory management circuit manages frame data for a display system such as used in a projection television system or cellular phone. The frame data includes frames corresponding to a series of images for viewing by a user. The memory manager includes an input buffer to receive the frame data, a memory interface coupled to receive the frame data from the input buffer, and an output buffer coupled to receive the frame data from the memory interface and output the frame data to a display such as a liquid crystal (LCD) micro-display. The memory interface sends and receives the frame data as packets, with each packet having a size less than a full frame, to and from an external memory able to store at least one full frame of data.

Claims

1. A memory manager to manage frame data for a display system, wherein the frame data comprises a frame corresponding to an image, the memory manager comprising:

an input buffer to receive the frame data;

a memory interface coupled to receive the frame data from the input buffer;

an output buffer coupled to receive the frame data from the memory interface and output the frame data; and

wherein the memory interface is operable to send and receive the frame data, as a plurality of packets with each packet having a size less than a full frame, to and from a memory operable to store the frame data.

2. The memory manager of claim 1 wherein the frame data is received by the input buffer at a rate of at least 20 full frames per second.

3. The memory manager of claim 1 wherein the image is a still image.

4. The memory manager of claim 1 wherein the size of each packet is less than about 20 percent of the total size for the full frame.

5. The memory manager of claim 1 wherein the size of each packet is less than five lines in the image.

6. The memory manager of claim 1 wherein the size of each packet is about one line in the image.

7. The memory manager of claim 1 wherein the frame data is frames of video data.

8. The memory manager of claim 1 wherein the memory is operable to store at least one and a half full frames of data.

9. The memory manager of claim 1 wherein the memory is operable to store at least two full frames of data.

10. The memory manager of claim 8 wherein:

the image is a first image of a series of images and the frame corresponding to the image is a first frame;

the frame data comprises a second frame corresponding to a second image of the series of images; and

the memory interface is further operable to alternately read a first portion of the first frame from the memory and write a first portion of the second frame to the memory.

11. The memory manager of claim 10 wherein the first portion of the first frame comprises two packets of data.

12. The memory manager of claim 11 wherein each of the two packets of data corresponds to a single line in the first image.

13. The memory manager of claim 11 wherein the first portion of the second frame corresponds to one packet of data.

14. The memory manager of claim 13 wherein the one packet of data corresponds to a single line in the second image.

15. The memory manager of claim 10 wherein the first portion of the first frame comprises three packets of data.

16. The memory manager of claim 15 wherein each of the three packets of data corresponds to a single line in the first image.

17. The memory manager of claim 10 wherein the memory interface is further operable to read a second portion of the first frame from the memory after writing the first portion of the second frame.

18. The memory manager of claim 1 wherein:

the image is a first image of a series of images and the frame corresponding to the image is a first frame;

the frame data comprises a second frame corresponding to a second image of the series of images; and

the memory interface is further operable to read the full first frame from the memory at least two times substantially during the same time period corresponding to writing the full second frame to the memory.

19. The memory manager of claim 1 wherein the output buffer is coupled to provide the frame data to a display for generating the image.

20. The memory manager of claim 1 wherein the input buffer is a first-in first-out (FIFO) memory.

21. The memory manager of claim 20 wherein the output buffer is a first-in first-out (FIFO) memory.

22. The memory manager of claim 1 wherein the input buffer is operable to store no more than five lines of the image.

23. The memory manager of claim 22 wherein the output buffer is operable to store no more than five lines of the image.

24. The memory manager of claim 1 wherein:

the smallest packet of the plurality of packets has a packet size; and

the input buffer is operable to store no more data than five times the packet size.

25. The memory manager of claim 1 wherein:

the smallest packet of the plurality of packets has a packet size; and

the input buffer is operable to store no more data than about one and a half times the packet size.

26. The memory manager of claim 1 wherein timing of the transfer of the plurality of packets between the input buffer, memory, and output buffer is controlled by a first clock.

27. The memory manager of claim 26 wherein timing of the receiving of the frame data by the input buffer is controlled by a second clock that is independent of the first clock.

28. The memory manager of claim 27 wherein timing of the outputting of the frame data by the output buffer is controlled by a third clock that is independent of the first clock and second clock.

29. The memory manager of claim 1 wherein:

the output buffer is coupled to a look-up table;

the look-up table is coupled to provide the frame data to a plurality of digital-to-analog converters (DACs); and

the plurality of DACs is coupled to provide the frame data to a display for generating the image.

30. The memory manager of claim 1 wherein the memory is a dual data rate synchronous dynamic random access memory.

31. The memory manager of claim 1 wherein the memory interface addresses the memory in an always increasing incremental manner of memory addressing during the reading or writing of data at least until a frame has been fully read or written.

32. A display system to manage data, wherein the data comprises a plurality of frames with each frame corresponding to one of a plurality of images, the display system comprising:

an input buffer to receive the data as a plurality of packets;

a memory interface coupled to receive the plurality of packets from the input buffer;

an output buffer coupled to receive the plurality of packets from the memory interface and output the plurality of packets; and

wherein the memory interface is operable to read and write the data to and from a memory as a plurality of packets with each packet having a size less than a full frame, the memory being operable to store at least one and a half full frames.

33. The display system of claim 32 wherein the memory interface is operable to alternately read and write the plurality of packets, for at least five total packets read and at least five total packets written for a single frame, in less time than required for the output buffer to output a full frame.

34. The display system of claim 33 wherein each of the plurality of packets has the size of about a video line of data.

35. A display system comprising:

a screen for a user to view images;

a display to generate the images;

an optical system coupling the display to the screen;

a memory manager, wherein the memory manager comprises;

(i) an input buffer to receive frame data corresponding to the images; and

(ii) an output buffer to provide the frame data to the display; and

a memory coupled to receive the frame data from the input buffer and to provide the frame data to the output buffer, wherein;

(i) the frame data comprises data for a first frame and a second frame;

(ii) a first portion of the first frame is stored in the memory; and

(iii) a first portion of the second frame is read from the memory after storing the first portion of the first frame in the memory; and

(iv) a second portion of the first frame is stored in the memory after reading the first portion of the second frame from the memory.

36. The display system of claim 35 wherein the display system is a projection television system.

37. The display system of claim 35 wh ere in the memory is a random access memory.

38. The display system of claim 35 wherein the display system is selected from the group consisting of:

a projector, a personal computer monitor, a digital photographic development system, an optical data storage system, and an x-ray projector/display system.

39. A display system comprising:

a display for a user to view images;

a display coupled to receive frame data to form the images;

a memory manager, wherein the memory manager comprises;

(i) an input buffer to receive the frame data;

(ii) an output buffer to provide the frame data to the display; and

a memory coupled to receive the frame data from the input buffer and to provide the frame data to the output buffer, wherein;

(i) the frame data comprises data for a first frame and a second frame;

(ii) a first portion of the first frame is stored in the memory; and

(iii) a first portion of the second frame is read from the memory after storing the first portion of the first frame in the memory; and

(iv) a second portion of the first frame is stored in the memory after reading the first portion of the second frame from the memory.

40. The display system of claim 39 wherein the display system is a cellular phone.

41. The display system of claim 39 wherein the display system is a portable computing device.

42. A method of managing frame data for use in a display system, wherein the frame data comprises a first frame and a second frame, the method comprising:

(a) reading a first portion of a first frame from a memory operable to store at least one full frame of the frame data;

(b) after reading the first portion of the first frame, writing a first portion of the second frame to the memory; and

(c) after writing the first portion of the second frame to the memory, reading a second portion of the first frame from the memory.

43. The method of claim 42 further comprising alternately repeating items (a) and (b) each at least ten times, for additional portions of the first frame and the second frame, prior to writing the entire second frame to the memory.

44. The method of claim 42 further comprising:

writing the entire second frame to the memory in a time period; and

reading the entire first frame at least two times from the memory substantially during same time period.

45. The method of claim 42 wherein:

the memory is partitioned into a first partition and a second partition;

the first frame is stored fully within the first partition; and

the second frame is stored fully within the second partition.

46. The method of claim 45 wherein:

the first frame is accessed in the memory using a plurality of memory addresses; and

the first frame is read from the memory by continuously incrementing or decrementing through the plurality of memory addresses.

47. The method of claim 46 wherein the plurality of memory addresses comprises a starting address and an ending address for the first frame.

48. The method of claim 47 wherein the starting address and the ending address are within the address space of the first partition.

49. A computer-readable medium having computer-executable instructions for performing the method of claim 42.

50. The computer-readable medium of claim 49 wherein the computer-readable medium is selected from the group consisting of:

a floppy disk, a hard drive, a CD-ROM, and a RAM.

51. A method of managing frame data for use in a display system, wherein the frame data comprises a first frame, a second frame, a third frame, and a fourth frame, the method comprising:

writing the first frame to a memory operable to store at least one full frame, but less than two full frames, of the frame data, wherein the first frame is stored in the memory starting at a first starting address;

writing the second frame to the memory, wherein the second frame is the next frame written to the memory after the first frame and is stored in the memory starting at a second starting address different from the first starting address;

writing the third frame to the memory, wherein the third frame is the next frame written to the memory after the second frame and is stored in the memory starting at a third starting address different from the first and second starting addresses; and

writing the fourth frame to the memory, wherein the fourth frame is the next frame written to the memory after the third frame and is stored in the memory starting at the first starting address.

52. A method of storing frame data for use in a display system, the method comprising consecutively writing a plurality of frames, corresponding to a series of images for display to a user, to a memory wherein the memory address space of the memory used to write a first frame of the plurality of frames is common with at least a portion of the memory address space used to write a second frame of the plurality of frames.

53. The method of claim 52 wherein:

starting addresses for writing each of the plurality of frames in the memory repeatedly cycle through at least first, second, and third address locations; and

the first, second, and third address locations are different.

54. The method of claim 52 further comprising consecutively reading the plurality of frames from the memory wherein starting addresses for reading each of the plurality of frames repeatedly cycle through the same at least first, second, and third address locations.

55. The method of claim 52 wherein reading a portion of the first frame from the memory and alternately writing a portion of the second frame to the memory are continuously repeated.

56. The method of claim 52 wherein each of the plurality of frames is written to the memory by incrementing or decrementing the memory address throughout the full storage location of each frame in the memory.

57. A method of storing frame data for use in a display system, the method comprising consecutively writing a plurality of frames, corresponding to a plurality of images for display to a user, to a memory wherein:

starting addresses for writing each of the plurality of frames in the memory repeatedly cycle through at least first, second, and third address locations; and

the first, second, and third address locations are different.

58. The method of claim 57 wherein the starting addresses repeatedly cycle through five different address locations.

59. The method of claim 58 wherein the memory is operable to store at least one full frame, but less than two full frames, of the frame data.

60. The method of claim 57 wherein the plurality of images are displayed to the user at a frequency of at least about 60 images per second.

61. A memory manager to manage frame data for a display system, wherein the frame data comprises a first frame corresponding to a first image of a series of video images, the memory manager comprising:

an input buffer to receive the frame data;

a memory interface coupled to receive the frame data from the input buffer;

an output buffer coupled to receive the frame data from the memory interface and output the frame data;

wherein the memory interface is operable to send and receive the frame data, as a plurality of packets with each packet having a size less than a full frame, to and from a memory operable to store the frame data;

wherein the size of each packet is less than about 20 percent of the total full frame size; and

wherein the memory is operable to store at least one and a half full frames of video data.

62. The memory manager of claim 61 wherein the memory is operable to store at least two full frames of data.

63. The memory manager of claim 61 wherein:

the frame data comprises a second frame corresponding to a second image of the series of images; and

the memory interface is further operable to alternately read a portion of the first frame from the memory and write a portion of the second frame to the memory.

64. The memory manager of claim 63 wherein:

each of the plurality of packets has a packet size; and

the input buffer is operable to store no more data than five times the packet size.

65. The memory manager of claim 64 wherein:

the output buffer is coupled to a look-up table;

the look-up table is coupled to provide the frame data to a plurality of digital-to-analog converters (DACs); and

the plurality of DACs is coupled to provide the frame data to a display for generating the series of images.

66. The memory manager of claim 61 wherein the frame data is received by the input buffer at a rate of at least 20 full frames per second.