Electronics for a shock hardened data recorder

• US 20030223317A1
• Filed: 03/17/2003
• Published: 12/04/2003
• Est. Priority Date: 06/02/2000
• Status: Active Grant

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Haddon, Michael D., Soto, Gabriel H.
• Granted Patent: US 6,782,298 B2
• Time in Patent Office: Days
• US Class Current: 369/29.02
• CPC Class Codes: G05B 19/00 Programme-control systems

Abstract

Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high MTBF (mean time between failure) figures in more benign environments.

Claims

1. A method for recording data on a recorder that experiences physical shock, power disruption, or both, comprising:

conditioning a signal;

powering components of the digital recorder using said conditioned signal;

establishing and providing a reference time;

converting input analog signals into digital form as bytes of data;

separating said bytes into a most significant byte and a least significant byte;

controlling operations on said bits using said reference time and a trigger signal;

serially transmitting said separated bytes;

storing said separated bytes in non-volatile memory;

recombining said separated bytes; and

outputting said recombined bytes,

wherein said method provides a reliable and efficient means for acquiring, recording, and outputting data obtained while testing in unfavorable environmental conditions.

2. The method of claim 1, said signal conditioning further comprising:

regulating voltage via a voltage regulator having an input and an output;

providing a source of energy via a first capacitance and a second capacitance operably connected to said regulator'"'"'s input and output, respectively;

suppressing voltage spikes via a diode operably connected to said voltage regulator'"'"'s output of said signal conditioning circuit and electrical ground; and

providing one way isolation via a diode imposed between the input of said signal conditioning circuit and the power connection,

wherein said signal-conditioning provides filtered and regulated power to said recorder.

3. The method of claim 1, said timing provided via an oscillator having a third capacitor operably connected thereto.

4. The method of claim 1, converting an analog input signal to 16-bit words via a 16-bit ADC.

5. The method of claim 1, controlling the timing, processing, storage, and transmitting of said 16-bit words via a field programmable gate array (FPGA).

6. The method of claim 1, further comprising:

storing said data within said non-volatile memory consisting essentially of electronically erasable programmable read only memories (EEPROMs) and fast static random access memories (SRAMs), at least one of each of said EEPROMs and said SRAMs configured on each of a first and second memory chip,

receiving input from said controller to said non-volatile memory in the form of two 8-bit bytes, a first 8-bit byte consisting of a most significant byte and a memory address, and a second 8-bit byte consisting of a least byte and a memory address, and

reading said most significant byte into said first memory chip and said least significant byte into said second memory chip in the order of most significant byte first and least significant byte second.

7. The method of claim 1 further comprising:

providing fourth through ninth capacitors, each of said fourth through ninth capacitors imposed between an electrical ground and said signal conditioning circuit, said timing source, said analog-to-digital converter (ADC), said trigger,

said controller, and said non-volatile memory, respectively,

wherein said fourth through ninth capacitors provide for the orderly shutdown and power up of said recorder in the event of a power loss.