Method and system for deterministic control of an emulation

• US 20030225560A1
• Filed: 03/12/2003
• Published: 12/04/2003
• Est. Priority Date: 06/03/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Garcia, Luis, Novak, Christopher B., Roussel, Christopher A., Vreeland, Russell E., Marasigan, Gabriel G.
• Granted Patent: US 7,440,885 B2
• Time in Patent Office: Days
• US Class Current: 703/17
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Claims

1. An emulation-based event-wait simulator comprising:

an application module that configures verification processes on a design under test (DUT);

an event dispatcher in communication with the application module, that forwards commands to the DUT;

a plurality of transactors in communication with the event dispatcher, that receive the commands and deliver the commands to the DUT; and

a channel controller in communication with the transactors, that processes and forwards the commands to the transactors, wherein the channel controller also receives response messages from the transactors, processes the response messages, and forwards the response messages to the transactors for delivery to the event dispatcher and the application module.

2. The system of claim 1, wherein the operations of the DUT can be halted to an accuracy of one processing cycle.

3. The system of claim 1, further including a controlled clock, wherein the application module provides information to the channel controller indicating how many cycles the controlled clock should run for.

4. The system of claim 3, wherein the application module sends data to the DUT such that data is transferred to the DUT on a plurality of I/O channels simultaneously when the clock is restarted after being stopped.

5. The system of claim 1, wherein the channel controller communicates status of a deterministically controlled clock to the application module over an interface.

6. The system of claim 5, wherein the clock is advanced by a number of cycles received in a command from the application module.

7. The system of claim 1, wherein the channel controller sends priority encoded messages to the application module.

8. A system for evaluating performance of a device under test (DUT) comprising:

a deterministic emulator including a channel controller that receives data packets from an application module; and

a plurality of transactors forwarding the data packets to corresponding output channels to be transferred to the DUT.

9. The system of claim 8, wherein the application module provides information to the deterministic emulator indicating how many cycles a clock within the emulator should run for.

10. The system of claim 9, wherein the application module sends data to the deterministic emulator such that data is transferred to the DUT on a plurality of I/O channels simultaneously when the clock is restarted after being stopped.

11. The system of claim 8, further including a channel controller that communicates status of a deterministically controlled clock to the application module for keeping track of emulation time.

12. The system of claim 11, wherein the deterministically controlled clock is advanced by a number of cycles received in a command from the application module.

13. A system that deterministically evaluates operations of a circuit design comprising:

an application module that determines a set of commands for execution by a design under test (DUT);

a channel controller that delivers the set of commands to the DUT; and

an event dispatcher that receives a set of events from the DUT that includes results of the execution of the set of commands.

14. The system of claim 13, further including a source level debugger that monitors the DUT during the execution of the set of commands, wherein the source level debugger determines the occurrence of an event-wait condition, halts the operation of the DUT, measures the event-wait condition, and resumes the operation of the DUT.

15. A system that deterministically evaluates operations of a circuit design comprising:

an application module that defines commands and test vectors for execution by a design under test (DUT);

a channel controller that delivers the commands and the test vectors to the DUT;

a source level debugger that monitors the DUT during the execution of the commands;

an event dispatcher that receives events from the DUT, wherein the events includes results of the execution of the commands.

16. A method for deterministically evaluating operations of a circuit design comprising:

determining a first set of commands for execution by a design under test (DUT);

delivering the first set of commands to the DUT;

monitoring the DUT during the execution of the first set of commands;

receiving a first set of events from the DUT wherein the first set of events includes results of the execution of the first set of commands; and

determining, from the first set of events, a second set of commands for execution by the DUT, wherein the second set of commands tests one or more operations performed by the DUT.

17. The method of claim 16, wherein the monitoring step further comprises:

determining an occurrence of an event-wait condition;

halting an operation of the DUT;

measuring the event-wait condition; and

resuming the operation of the DUT.

18. A method for simulating events in an emulation-based environment comprising:

configuring verification commands for a design under test (DUT);

forwarding the verification commands to the DUT through a plurality of transactors;

receiving response messages from the DUT;

processing the response messages from the DUT; and

forwarding the response messages to the transactors.

19. The method of claim 18, further including:

detecting an occurrence of an event-wait condition;

halting operation of the DUT;

measuring the event-wait condition; and

resuming the operation of the DUT.

20. The method of claim 18, wherein the operations of the DUT are halted after one or more processing cycles.

21. The method of claim 20, further including providing information to the emulation-based environment indicating how many cycles a controlled clock in the emulation-based environment should run for, the controlled clock being used as a clock input for the DUT.

22. The method of claim 21, further including sending data to the DUT such that data is transferred to the DUT on a plurality of I/O channels simultaneously when the controlled clock in the emulation-based environment is restarted after being stopped.

23. The method of claim 21, wherein the controlled clock runs in a deterministic manner.

24. A method for deterministically evaluating operations of a circuit design comprising:

determining a first set of commands for execution by the circuit design;

delivering the first set of commands to the circuit design;

monitoring the circuit design during the execution of the first set of commands;

receiving a first set of events from the circuit design wherein the first set of events includes results of the execution of the first set of commands; and

determining, from the first set of events, a second set of commands for execution by the circuit design, wherein the second set of commands tests one or more operations performed by the circuit design.