Image sensor

• US 20030227040A1
• Filed: 04/01/2003
• Published: 12/11/2003
• Est. Priority Date: 04/02/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Henderson, Robert
• Granted Patent: US 7,280,140 B2
• Time in Patent Office: Days
• US Class Current: 257/291
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A solid state image sensor has an array of pixels in which each column has a reset voltage line and a read line. The sensor is reset and read a row at a time, with reset-related values held in a frame buffer for subsequent subtraction from read values. Reset-related values are derived in each column by sampling the voltage during reset on one capacitor and the voltage on release of reset on a second capacitor, and differencing these values to provide an output for the frame buffer. This provides a reduction in the size of frame buffer which would otherwise be required.

Claims

1. A method of operating an image sensor, the image sensor having an array of pixels arranged in rows and columns;

the method comprising;

reading reset-related values from the pixels a row at a time and storing these values in a frame store;

reading signal-related values from the pixels a row at a time, interleaved with reading of the rows of signal-related values;

the reading of said two values for a given row being offset by a number of row periods selected to control the exposure of the image sensor;

and subtracting the reset-related value for each pixel from the signal-related value of the same pixel to give an output signal for that pixel;

and in which the reset-related values stored in the frame store are produced by differencing two pixel values which are sampled and stored during reset and on release from reset, respectively; and

the signal-related values are produced by differencing the pixel values stored during reset and after exposure, respectively.

2. The method of claim 1, in which each pixel contains a source follower transistor and said differencing is effective to eliminate from the stored value the effect of the source follower gate-source voltage.

3. The method of claim 1 or claim 2, including the further step of subtracting a DC offset voltage from the black reference voltage during sampling.

4. An image sensor comprising an array of pixels arranged in rows and columns, each pixel comprising a photosensitive element and switching means operable to apply a reset voltage to the photosensitive element and to read signal voltages therefrom;

the image sensor further comprising timing and storage means operable to sample and hold pixel values during reset and release from reset, respectively,

and a difference circuit arranged to output to a frame store the difference between said sampled values as a reset-related value for each pixel.

5. An image sensor according to claim 4, in which the timing and storage means is also operable to sample and hold pixel values during reset and after exposure, respectively, which values are differenced by the difference circuit to form a signal-related value for each pixel;

and the image sensor further including said frame store, and means for subtracting for each pixel its reset-related value retrieved from the frame store from its signal-related value.

6. An image sensor according to claim 4 or claim 5, in which each column of the array has a readout line connectable by a pair of switches to a pair of sample capacitors, said capacitors forming the input to said difference circuit.

7. An image sensor according to claim 6, including means for applying a DC offset voltage to one of said capacitors which in use holds a reset-related value.

8. An image sensor according to claim 7, in which analogue-to-digital conversion is provided by a ramp generator arranged to apply a ramp voltage to the other capacitor.