High speed interconnect circuit test method and apparatus
First Claim
Patent Images
1. A test access port comprising:
- a test clock input;
a test mode select input;
a test data in input;
a test data out output;
a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, an Update-DR signal, and a Shift-DR signal, and having a control bus input;
an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output;
a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;
a delay circuit connected to the test clock input and having a delayed clock output; and
propagation test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the propagation of functional signals received by the boundary scan register.
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Abstract
A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.
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Citations
6 Claims
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1. A test access port comprising:
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a test clock input;
a test mode select input;
a test data in input;
a test data out output;
a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, an Update-DR signal, and a Shift-DR signal, and having a control bus input;
an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output;
a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;
a delay circuit connected to the test clock input and having a delayed clock output; and
propagation test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the propagation of functional signals received by the boundary scan register.
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2. A test access port comprising:
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a test clock input;
a test mode select input;
a test data in input;
a test data out output;
a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, an Update-DR signal, and a Shift-DR signal, and having a control bus input;
an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output and a test signal output;
a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, the Update-DR signal and the Shift-DR signal, the boundary scan register having a modified Clock-DR input;
a delay circuit connected to the test clock input and having a delayed clock output; and
decay test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, and the modified Clock-DR input to test the RC time decay of functional signals received by the boundary scan register.
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3. A test access port comprising:
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a test clock input;
a test mode select input;
a test data in input;
a test data out output;
a controller connected to the test clock input and the test mode select input, the controller providing an Update-DR signal, a Clock-DR signal, an Update-DR signal, and a Shift-DR signal, and having a control bus input;
an instruction register connected to the test data in input and the test data out output and having a control bus output connected to the controller, the instruction register also having a mode signal output and a test signal output;
a boundary scan register connected to functional data signals, the test data in input, the test data out output, the mode signal output, the test signal output, and the Shift-DR signal, the boundary scan register having a modified Clock-DR input, a toggle input a flag input and a modified Update-DR input;
a delay circuit connected to the test clock input and having a delayed clock output; and
cycle test circuitry connected to the delayed clock output, the control bus, the Update-DR signal, the Clock-DR signal, the modified Clock-DR input, the modified Update-DR input, the toggle input, and the flag input to test toggled functional signals received by the boundary scan register.
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4. A process of performing a test comprising:
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applying a test data signal at the input of an interconnect circuit, which has an output, at a defined time during an Update-DR state of a JTAG test access port controller;
performing a sample of the test data signal at the interconnect circuit output under at least partial control of a JTAG test access port controller at a selectable time after the defined time, the selectable time occurring before a normal sample of the test data signal during a Capture-DR state of the controller that normally follows the Update-DR state; and
preventing the normal sample of the test data signal at the output of the interconnect circuit under at least partial control of the JTAG test access port controller during the Capture-DR state that normally follows the Update-DR state.
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5. A process of performing a test comprising:
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applying a test data signal at the input of an interconnect circuit, which has an output, for a period of time starting at a defined time during an Update-DR state, occurring in a JTAG test access port controller, that is later followed by a Capture-DR state;
performing a first sample of the test data signal at the interconnect circuit output under at least partial control of a JTAG test access port controller at a selectable time that is after the defined time and before the Capture-DR state; and
performing a second sample of the test data signal at the output of the interconnect circuit under at least partial control of the JTAG test access port controller during the first Capture-DR state of the controller normally occurring after the Update-DR state.
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6. A method of testing an interconnect circuit between a first and second device comprising the steps of;
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applying, from the first device, a stimulus signal to the interconnect circuit;
observing, in the second device, the transient response of the interconnect circuit to the stimulus signal under at least partial control of a JTAG test access port controller, and observing, in the second device, the steady state response of the interconnect circuit to the stimulus signal under at least partial control of a JTAG test access port controller.
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Specification