Signal sharing circuit with microelectronic die isolation features

• US 20030235929A1
• Filed: 06/20/2002
• Published: 12/25/2003
• Est. Priority Date: 06/20/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Granted Patent: US 6,967,348 B2
• Time in Patent Office: Days
• US Class Current: 438/17
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal.

Claims

1. A signal sharing circuit, comprising:

a first pad adapted to receive a signal; and

a first sharing device associated with a first microelectronic die and adapted to selectively share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal.

2. The signal sharing circuit of claim 1, further comprising a second sharing device associated with the first microelectronic die and adapted to selectively share the signal with at least a third microelectronic die on another side of the first microelectronic die in response to a second share control signal.

3. The signal sharing circuit of claim 2, further comprising:

a part pad coupled to each microelectronic die; and

an isolation device associated with each microelectronic die and adapted to apply the signal to the part pad of each microelectronic die in response to an associated isolation control signal.

4. The signal sharing circuit of claim 3, further comprising:

a third sharing device associated with the second microelectronic die and adapted to couple the signal to the isolation device associated with the second microelectronic die in response to a third share control signal; and

a fourth sharing device associated with the second microelectronic die and adapted to selectively share the signal with at least one other microelectronic die on another side of the second microelectronic die from the first microelectronic die in response to a fourth share control signal.

5. The signal sharing circuit of claim 4, further comprising:

a fifth sharing device associated with the third microelectronic die and adapted to couple the signal to the isolation device associated with the third microelectronic die in response to a fifth share control signal; and

a sixth sharing device associated with the third microelectronic die and adapted to selectively share the signal with at least one other microelectronic die on another side of the third microelectronic die from the first microelectronic die in response to a sixth share control signal.

6. A signal sharing circuit comprising:

a pad adapted to receive one of a signal, power or ground potential; and

a plurality of sharing devices, at least one sharing device associated with each one of a plurality of microelectronic dies to selectively share the signal, power or ground potential with other dies of the plurality of microelectronic dies.

7. A signal sharing circuit, comprising:

a first pad adapted to receive a signal;

a part pad coupled to a first microelectronic die; and

an isolation device adapted to transfer the signal from the first pad to the part pad in response to an isolation control signal.

8. The signal sharing circuit of claim 7, further comprising a sharing device to share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a share control signal.

9. The signal sharing circuit of claim 8, further comprising another sharing device to share the signal with at least a third microelectronic die on another side of the first microelectronic die in response to another share control signal.

10. The signal sharing circuit of claim 7, further comprising at least one other isolation device associated with at least one other microelectronic die and adapted to couple the signal to the other microelectronic die in response to another isolation signal.

11. A signal sharing circuit, comprising:

a first pad adapted to receive a signal;

a part pad coupled to a first microelectronic die;

an isolation device adapted to transfer the signal from the first pad to the part pad in response to an isolation control signal; and

an isolation control circuit to provide the isolation control signal.

12. The signal sharing circuit of claim 11, wherein the isolation control circuit comprises:

a probe pad to receive a control signal; and

a programmable device adapted to selectively disconnect or connect the probe pad to the isolation device.

13. The signal sharing circuit of claim 12, wherein the programmable device is one of metal oxide semiconductor (MOS) device, a multiplexor, a conductive jumper, a ball-bond, a fuse type device or an anti-fuse type device.

14. The signal sharing circuit of claim 12, wherein the isolation circuit further comprises another device to selectively prevent the probe pad from being coupled to the part pad during a predetermined use of the microelectronic die.

15. The signal sharing circuit of claim 11, wherein the isolation control circuit comprises a circuit to provide a signal to selectively turn off the first microelectronic die.

16. The signal sharing circuit of claim 15, wherein the circuit to provide a signal to selectively turn off the first microelectronic die comprises:

a first probe pad adapted to receive a first control signal;

a first MOS device of one type including a gate coupled to the first probe pad;

a second MOS device of another type including a gate coupled to the first probe pad and a first terminal coupled to a first terminal of the first MOS device and a second terminal connected to ground potential;

a second probe pad adapted to receive a second control signal;

a logic gate including one input coupled to the second probe pad and a second input coupled to the first terminal of the first MOS device and to the first terminal of the second MOS device and an output connected to the first microelectronic die to provide the signal to selectively turn power off to the first microelectronic die;

an inverter including an input coupled to the second probe pad;

a third MOS device of the one type including a gate connected to an output of the inverter and a first terminal connectable to a high signal and a second terminal connected to a second terminal of the first MOS device; and

a fourth MOS device of the other type including a gate connected to the output of the inverter and a first terminal connected to the second terminals of the first and third MOS devices and a second terminal connected to ground.

17. A programmable signal sharing circuit, comprising:

a first pad adapted to receive a signal;

a part pad coupled to a first microelectronic die;

a isolation circuit adapted to transfer the signal from the first pad to the part pad in response to an isolation control signal;

a first sharing device adapted to couple the signal to a second microelectronic die on one side of the first microelectronic die in response to a first share control signal; and

a second sharing device adapted to couple the signal to a third microelectronic die on another side of the first microelectronic die in response to a second share control signal.

18. The programmable signal sharing circuit of claim 17, wherein the isolation circuit comprises at least one metal oxide semiconductor (MOS) device.

19. The programmable signal sharing circuit of claim 17, wherein each of the sharing devices comprise an MOS device.

20. The programmable signal sharing circuit of claim 17, wherein at least the first pad is adapted to be contacted by an external pin.

21. The programmable signal sharing circuit of claim 17, wherein at least the first pad is formed on one of a scribe area, the first microelectronic die, a mutant die or a sacrifice die.

22. A signal sharing circuit, comprising:

a first pad adapted to receive a signal;

a part pad coupled to a first microelectronic die;

a isolation circuit adapted to transfer the signal from the first pad to the part pad in response to an isolation control signal;

a first sharing device adapted to couple the signal to a second microelectronic die on one side of the first microelectronic die in response to a first share control signal;

a second sharing device adapted to couple the signal to a third microelectronic die on another side of the first microelectronic die in response to a second share control signal;

a first share control circuit to provide the first share control signal;

a second share control circuit to provide the second share control signal; and

an isolation control circuit to provide the isolation control signal.

23. The signal sharing circuit of claim 22, wherein the first and second share control circuits each comprise a receiving device to receive a control signal.

24. The signal sharing circuit of claim 23, wherein the receiving device comprises at least one of a probe pad, a radio frequency identification control (RFID) or a fuse type control.

25. The signal sharing circuit of claim 22, wherein the isolation circuit comprises:

a probe pad adapted to receive an isolation control signal; and

a programmable device to selectively disconnect or connect the probe pad to the isolation circuit.

26. The signal sharing circuit of claim 25, wherein the programmable device is one of an MOS device, a multiplexor, a conductive jumper, a ball-bond, a fuse type device and an anti-fuse type device.

27. A signal sharing circuit, comprising:

at least one pad adapted to receive a signal; and

a plurality of sharing devices, wherein at least one sharing device is associated with each one of a plurality of microelectronic dies to share the signal with an adjacent die in response to the at least one sharing device receiving a share control signal.

28. The signal sharing circuit of claim 27, further comprising:

a part pad coupled to each microelectronic die; and

an isolation circuit associated with each microelectronic die and adapted to apply the signal to the part pad of each microelectronic die in response to an associated isolation control signal.

29. The signal sharing circuit of claim 27, wherein a pair of sharing devices of the plurality of sharing devices is associated with each microelectronic die to selectively share the signal with dies on either side of each microelectronic die.

30. The signal sharing circuit of claim 27, wherein the microelectronic die is one of a memory chip or a processor chip and the signal is one of an address test signal, a command test signal or a data signal to test the memory chip or processor chip.

31. A microelectronic die, comprising:

a first pad adapted to receive a signal; and

a sharing device adapted to share the signal with at least a second microelectronic die in response to a share control signal.

32. The microelectronic die of claim 31, further comprising:

a part pad coupled to the microelectronic die; and

an isolation circuit adapted to apply the signal to the part pad in response to an isolation control signal.

33. The microelectronic die of claim 31, further comprising another sharing device to share the signal with at least a third microelectronic die.

34. The microelectronic die of claim 31, wherein the at least one sharing device is an MOS device.

35. A microelectronic die, comprising:

a multiplicity of probe pads each adapted to receive an associated test signal; and

a plurality of first sharing devices each coupled to a selected one of the multiplicity of probe pads to selectively share the associated test signal with at least a second microelectronic die in one direction relative to the microelectronic die in response to each first sharing device receiving an associated share control signal.

36. The microelectronic die of claim 35, further comprising a plurality of second sharing devices each coupled to an associated one of the plurality of first sharing devices to selectively share the associated test signal in another direction relative to the microelectronic die in response to each second sharing device receiving another associated share control signal.

37. The microelectronic die of claim 35, further comprising an isolation circuit adapted to apply the signal to the microelectronic die in response to an isolation control signal.

38. A semiconductor wafer, comprising:

a plurality of microelectronic dies;

a first pad adapted to receive a signal; and

at least one sharing device associated with each of the plurality of microelectronic dies adapted to share the signal in one direction from each of the plurality of microelectronic dies in response to a share control signal.

39. The semiconductor wafer of claim 38, further comprising a second sharing device associated with each microelectronic die adapted to share the signal in another direction from each of the plurality of microelectronic dies in response to a second share control signal.

40. The semiconductor wafer of claim 39, further comprising a conductive line formed in a redistribution layer to connect the at least one sharing device associated with each microelectronic die to the second sharing device associated with an adjacent microelectronic die.

41. The semiconductor wafer of claim 38, further comprising:

a part pad coupled to each of the plurality of microelectronic dies; and

an isolation device associated with each of the plurality of microelectronic dies and adapted to apply the signal to the part pad in response to an associated isolation control signal.

42. The semiconductor wafer of claim 38, wherein the first pad is formed on one of a scribe, one of the plurality of microelectronic dies, a mutant die or a sacrifice die.

43. A semiconductor wafer, comprising:

a plurality of microelectronic dies divided into groups of a chosen number of dies;

a set of test pads associated with each group of microelectronic dies, each test pad being adapted to receive a predetermined signal; and

at least one sharing device associated with each of selected ones of the plurality of test pads and associated with each microelectronic die to selectively share the predetermined signal with other microelectronic dies in response to a first share control signal.

44. The semiconductor wafer of claim 43, further comprising a second sharing device associated with each of the selected ones of the plurality of test pads and associated with each microelectronic die to selectively share the predetermined signal with other microelectronic dies in response to a second share control signal, wherein the at least one sharing device shares the predetermined signal in one direction and the second sharing device shares the predetermined signal in another direction.

45. The semiconductor wafer of claim 44, further comprising:

a first share control circuit associated with each at least one sharing device to provide the first share control signal; and

a second share control circuit associated with each second sharing device to provide the second share control signal.

46. The semiconductor wafer of claim 45, wherein each of the first and second share control circuits comprise:

a probe pad adapted to receive a share control signal; and

a programmable device to selectively connect or disconnect the probe pad from an associated one of the first and second share devices.

47. The semiconductor wafer of claim 46, wherein each of the first and second share control circuits further comprise another device to selectively prevent the probe pad from being coupled to the microelectronic die during a predetermined use of the microelectronic die.

48. The semiconductor wafer of claim 43, further comprising:

a part pad coupled to each microelectronic die;

an isolation device associated with each microelectronic die and adapted to apply the predetermined signal to the part pad in response to an isolation control signal; and

an isolation control circuit associated with each isolation device to provide the isolation control signal.

49. The semiconductor wafer of claim 48, wherein each isolation control circuit comprises:

a probe pad to receive a control signal; and

a programmable device adapted to selectively disconnect or connect the probe pad to the isolation device.

50. The semiconductor wafer of claim 49, wherein each isolation circuit further comprises another device to selectively prevent the probe pad from being coupled to the part pad during a predetermined use of the microelectronic die.

51. The semiconductor wafer of claim 43, wherein the test pads are formed on one of a scribe, one of the microelectronic dies in each group, a mutant die or a sacrifice die.

52. An electronic system, comprising:

a processor; and

a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die, the microelectronic die including at least one sharing device to share a signal in one direction from the microelectronic die.

53. The electronic system of claim 52, wherein the microelectronic die comprises a second a second share device to share the signal in another direction from the die.

54. The electronic system of claim 52, further comprising a device to prevent a probe pad from being coupled to the microelectronic die during a predetermined use of the of the electronic system.

55. An electronic system, comprising:

a processor; and

a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including a sharing circuit, the sharing circuit including;

a first pad to receive a test signal during testing of the system;

at least one share device to share the test signal in one direction from the microelectronic die; and

a second device to selectively prevent the first pad from being coupled to the microelectronic die during normal operations of the electronic system.

56. The electronic system of claim 55, wherein the microelectronic die comprises a second device to share the test signal in another direction from the microelectronic die.

57. The electronic system of claim 55, wherein the microelectronic die comprises an isolation circuit to apply the test signal to a part pad coupled to the microelectronic die in response to an isolation control signal.

58. A module, comprising:

a plurality of microelectronic dies; and

at least one signal sharing circuit interconnecting each of the plurality of microelectronic dies.

59. The module of claim 58, wherein at least a portion of the plurality of microelectronic dies are taken as a group from a common semiconductor wafer.

60. The module of claim 58, wherein at least portions the signal sharing circuit are formed in an interconnect layer of a semiconductor wafer.

61. The module of claim 58, further comprising an isolation circuit associated with each microelectronic die.

62. A method of making a signal sharing circuit, comprising:

forming a first pad adapted to receive a signal; and

forming a first share device associated with a first microelectronic die adapted to share the signal with at least a second microelectronic die on one side of the first microelectronic die.

63. The method of claim 62, further comprising forming a second sharing device to share the signal with at least a third microelectronic die on another side of the first microelectronic die.

64. The method of claim 62, further comprising:

forming a part pad coupled to each microelectronic die; and

forming an isolation device associated with each microelectronic die.

65. A method of making a signal sharing circuit, comprising:

forming a first pad adapted to receive a control signal;

forming a first share device associated with a first microelectronic die adapted to share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal; and

forming a first share control circuit to provide a first share control signal.

66. The method of claim 65, further comprising:

forming a second share device associated with the first microelectronic die adapted to share the signal with at least a third microelectronic die on another side of the first microelectronic die in response to a second share control signal; and

forming a second share control circuit to provide a second share control signal.

67. A method of making a microelectronic die, comprising:

forming a first pad adapted to receive a signal; and

forming a sharing device adapted to share the signal with at least a second microelectronic die.

68. The method of claim 67, further comprising forming another sharing device to share the signal with at least a third microelectronic die.

69. The method of claim 67, wherein forming each sharing device comprises forming an MOS device.

70. A method of making a microelectronic die, comprising:

forming a multiplicity of probe pads each adapted to receive an associated signal; and

forming a plurality of first sharing devices each coupled to a selected one of the multiplicity of probe pads to selectively share the associated signal with at least a second microelectronic die in one direction from the microelectronic die in response to receiving an associated share control signal.

71. The method of claim 70, further comprising forming a plurality of second sharing device, each associated with one of the plurality of first sharing devices to selectively share the associated test signal with at least a third microelectronic die in another direction from the microelectronic die in response to receiving another associated share control signal.

72. A method of making a semiconductor wafer, comprising:

forming a plurality of microelectronic dies;

forming a first pad adapted to receive a signal; and

forming at least one sharing device associated with each of the plurality of microelectronic dies adapted to share the signal in one direction from each of the plurality of microelectronic dies in response to a share control signal.

73. The method of claim 72, further comprising forming a second sharing device associated with each microelectronic die adapted to share the signal in another direction from each of the plurality of microelectronic dies in response to a second share control signal.

74. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an signal sharing circuit and wherein forming the signal sharing circuit includes forming at least a first share device associated with the microelectronic die adapted to share a signal in one direction relative to the microelectronic die.

75. The method of claim 74, further comprising forming a second sharing device adapted to share the signal in another direction relative to the microelectronic die.

76. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die wherein forming the electronic die includes;

forming a multiplicity of probe pads each adapted to receive an associated test signal; and

forming a plurality of first sharing devices each coupled to a selected one of the multiplicity of probe pads, wherein each first sharing device selectively shares the associated test signal in one direction relative to the microelectronic die in response to receiving an associated share control signal.

77. The method of claim 76, further comprising forming a plurality of second sharing devices each coupled to one of the plurality of first sharing devices, wherein each second sharing device selectively shares the associated test signal in another direction relative to the microelectronic die in response to receiving another associated share control signal.

78. A method of sharing a test signal across a semiconductor wafer, comprising:

applying the test signal to a test pad; and

operating a share device to share the test signal in one direction relative to a microelectronic die.

79. The method of claim 78, further comprising operating another share device to share the test signal in another direction relative to the microelectronic die.

80. The method of claim 79, wherein operating each of the share devices comprises sending a gate signal to operate a MOS transistor.

81. The method of claim 78, further comprising operating an isolation device to apply the test signal to the microelectronic die.

82. The method of claim 81, further comprising preventing the isolation device and the sharing device from operating during a predetermined use of the microelectronic die.

83. A method of sharing a test signal across a semiconductor wafer, comprising:

applying the test signal to a test pad; and

selectively sharing the test signal in at least one direction with a plurality of microelectronic dies.

84. The method of claim 83, wherein selectively sharing the test signal comprises operating at least one sharing device associated with each microelectronic die to share the test signal in one direction.

85. The method of claim 84, further comprising operating a second sharing device associated with each microelectronic die to share the test signal in another direction.

86. A method of making a module, comprising:

forming a plurality of microelectronic dies; and

forming at least one signal sharing circuit interconnecting each of the plurality of microelectronic dies.

87. The method of claim 86, wherein forming the plurality of microelectronic dies comprises:

forming at least a portion of the plurality of microelectronic dies on a common semiconductor wafer; and

mounting the plurality of microelectronic dies on a printed circuit board.

88. The method of claim 86, wherein forming the at least one signal sharing circuit comprises forming an interconnect layer on a semiconductor wafer.