Method and apparatus for maintaining data integrity using a system management processor

• US 20040003322A1
• Filed: 06/28/2002
• Published: 01/01/2004
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Collins, David L., Dupree, Steven Ray
• Granted Patent: US 6,889,341 B2
• Time in Patent Office: Days
• US Class Current: 714/27
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16

Abstract

The disclosed embodiments relate generally to providing increased data integrity in computer systems and, more particularly, to using a system management processor to maintain the integrity of stored information. A system management processor detects an attempt to reboot the computer system and holds the system processor or processors in a reset state. While the system processor or processors are held in the reset state, the system management processor checks data such as the system BIOS to identify corruption. If the data checked by the system management processor is not corrupted, the system processor or processors are removed from the reset state and allowed to continue normal operation. If the data checked by the system management processor is corrupted, the system management processor repairs the corrupted data before removing the system processor or processors from the reset state.

Claims

1. A system management device that supports a computer system having at least one system processor, the system management device comprising:

a system management processor adapted to;

detect a boot attempt of the computer system;

place the at least one system processor in a reset state;

determine whether a set of target data is valid or corrupted;

attempt to repair the set of target data and then release the at least one system processor from the reset state if the set of target data is corrupted; and

release the at least one system processor from the reset state if the set of target data is valid.

2. The system management device of claim 1 wherein the system management processor detects a boot attempt of the computer system by monitoring a power switch.

3. The system management device of claim 1 wherein the system management processor detects a boot attempt of the computer system by intercepting a request to boot interrupt.

4. The system management device of claim 3 wherein the request to boot interrupt is asserted according to the Advanced Programmable Interrupt Controller (APIC) protocol.

5. The system management device of claim 3 wherein the request to boot interrupt is asserted according to the System Advanced Programmable Interrupt Controller (SAPIC) protocol.

6. The system management device of claim 1 wherein the set of target data comprises at least a portion of the BIOS of the computer system.

7. The system management device of claim 1 wherein the system management processor is adapted to obtain replacement data over a network connection if the set of target data is corrupted.

8. A computer system that includes at least one system processor and a system management processor, the computer system comprising:

a core logic chipset adapted to exchange data with the at least one system processor and the system management processor;

at least one input/output device adapted to deliver input data from a user to the core logic chipset;

a video graphics controller connected to the core logic chipset;

a storage device that is adapted to store a set of target data; and

wherein the system management processor is adapted to;

detect a boot attempt of the computer system;

place the at least one system processor in a reset state;

determine whether the set of target data is valid or corrupted;

attempt to repair the set of target data and then release the at least one system processor from the reset state if the set of target data is corrupted; and

release the at least one system processor from the reset state if the set of target data is valid.

9. The computer system of claim 8 wherein the system management processor detects a boot attempt of the computer system by monitoring a power switch.

10. The computer system of claim 8 wherein the system management processor detects a boot attempt of the computer system by intercepting a request to boot interrupt.

11. The computer system of claim 10 wherein the request to boot interrupt is asserted according to the Advanced Programmable Interrupt Controller (APIC) protocol.

12. The computer system of claim 10 wherein the request to boot interrupt is asserted according to the System Advanced Programmable Interrupt Controller (SAPIC) protocol.

13. The computer system of claim 8 wherein the set of target data comprises at least a portion of the BIOS of the computer system.

14. The computer system of claim 8 wherein the system management processor is adapted to obtain replacement data over a network connection if the set of target data is corrupted.

15. A process for maintaining the integrity of a set of target data in a computer system, the computer system having at least one system processor, the method comprising the acts of:

detecting a boot attempt of the computer system;

placing the at least one system processor in a reset state;

determining whether the set of target data is valid or corrupted;

attempting to repair the set of target data and then releasing the at least one system processor from the reset state if the set of target data is corrupted; and

releasing the at least one system processor from the reset state if the set of target data is valid.

16. The process of claim 15 wherein the act of detecting a boot attempt comprises monitoring a power switch.

17. The process of claim 15 wherein the act of detecting a boot attempt comprises intercepting a request to boot interrupt that is asserted according to the Advanced Programmable Interrupt Controller (APIC) protocol.

18. The process of claim 15 wherein the act of detecting a boot attempt comprises intercepting a request to boot interrupt that is asserted according to the System Advanced Programmable Interrupt Controller (SAPIC) protocol.

19. The process of claim 15 wherein the set of target data comprises at least a portion of the BIOS of the computer system.

20. The process of claim 15 wherein the act of attempting to repair the set of target data comprises requesting replacement data over a network connection if the set of target data is corrupted.