Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses
First Claim
Patent Images
1. A method for testing a memory circuit, the method comprising:
- multiplying a first number in a sequence of deterministic pseudo-random numbers by a multiplier;
discarding all of the product of said act of multiplying except for a first plurality of low order bits representing a portion of said product, said first plurality of low order bits also representing a first memory address; and
testing a portion of said memory circuit represented by said first memory address.
6 Assignments
0 Petitions
Accused Products
Abstract
A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.
42 Citations
66 Claims
-
1. A method for testing a memory circuit, the method comprising:
-
multiplying a first number in a sequence of deterministic pseudo-random numbers by a multiplier;
discarding all of the product of said act of multiplying except for a first plurality of low order bits representing a portion of said product, said first plurality of low order bits also representing a first memory address; and
testing a portion of said memory circuit represented by said first memory address. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A method for testing a memory circuit, the method comprising:
-
generating a first number in a sequence of deterministic pseudo-random numbers, said first number representing a first portion of a first address within said memory circuit to be tested;
combining said first address portion with a second address portion to form said first address; and
testing a portion of said memory circuit represented by said first address. - View Dependent Claims (7, 8, 9, 10, 11, 12)
-
-
13. A method for forming a sequence of memory addresses, the method comprising:
-
multiplying an initial value by a multiplier;
discarding all of the product of said first multiplying operation except for a first plurality of low order bits;
forwarding said first plurality of low order bits to a memory address builder for forming a first memory address;
multiplying said first plurality of low order bits by said multiplier;
discarding all of the product of said second multiplying operation except for a second plurality of low order bits; and
forwarding said second plurality of low order bits to said memory address builder for forming a second memory address. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
-
-
30. A system for forming a sequence of memory addresses, the system comprising:
-
a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers; and
an address builder coupled to an output of said pseudo-random number generator for receiving said first plurality of bits and combining said first plurality of bits with a second plurality of bits, such that said combined first and second plurality of bits form a first memory address. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
-
-
42. A system for forming a memory address, the system comprising:
-
a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers, said first pseudo-random number representing at least a portion of a first memory address; and
a pattern eliminator coupled to said pseudo-random number generator and configured to receive at least a portion of said first plurality of low order bits and to remove a pattern that exists in said portion.
-
-
43. A memory card containing a system for forming a memory address, the system comprising:
-
a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers; and
an address builder coupled to an output of said pseudo-random number generator for receiving said first plurality of bits and combining said first plurality of bits with a second plurality of bits, such that said combined first and second plurality of bits form a first memory address. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
-
-
54. A memory card containing a system for forming a memory address, the system comprising:
-
a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers, said first pseudo-random number representing at least a portion of a first memory address; and
a pattern eliminator coupled to said pseudo-random number generator and configured to receive at least a portion of said first plurality of low order bits and to remove a pattern that exists in said portion.
-
-
55. A processor system, comprising:
-
a central processing unit;
a memory card coupled to said processor, said memory card containing a system for forming a memory address, the system comprising;
a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers; and
an address builder coupled to an output of said pseudo-random number generator for receiving said first plurality of bits and combining said first plurality of bits with a second plurality of bits, such that said combined first and second plurality of bits form a first memory address. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63, 64, 65)
-
-
66. A processor system, comprising:
-
a central processing unit;
a memory card coupled to said processor, said memory card containing a system for forming a memory address, the system comprising;
a pseudo-random number generator for generating a first plurality of bits representing a first pseudo-random number in a sequence of deterministic pseudo-random numbers, said first pseudo-random number representing at least a portion of a first memory address; and
a pattern eliminator coupled to said pseudo-random number generator and configured to receive at least a portion of said first plurality of low order bits and to remove a pattern that exists in said portion.
-
Specification