Nonvolatile semiconductor memory device

• US 20040007734A1
• Filed: 12/30/2002
• Published: 01/15/2004
• Est. Priority Date: 07/05/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Morishita, Fukashi, Kato, Hiroshi, Ueno, Shuichi, Noda, Hideyuki, Kuge, Shigehiro
• Granted Patent: US 7,157,773 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

Claims

1. A nonvolatile semiconductor memory device including a memory cell, comprising:

a semiconductor substrate;

a semiconductor layer, located above said semiconductor substrate, including a source region, a channel region and a drain region of said memory cell; and

a lower insulator film located between said semiconductor substrate and said semiconductor layer.

2. The nonvolatile semiconductor memory device according to claim 1, further comprising an insulator film on said channel region, wherein

said insulator film includes a first charge trap insulator film capable of trapping charges.

3. The nonvolatile semiconductor memory device according to claim 2, further including a gate electrode of said memory cell on said insulator film for applying a potential to said first charge trap insulator film for trapping charges.

4. The nonvolatile semiconductor memory device according to claim 3, wherein

said insulator film has a multilayer structure of a first insulator film, said first charge trap insulator film and a second insulator film, and

said lower insulator film has a multilayer structure of a third insulator film, a second charge trap insulator film for trapping charges and a fourth insulator film.

5. The nonvolatile semiconductor memory device according to claim 4, wherein

at least either said first charge trap insulator film or said second charge trap insulator film is made of a nitride film.

6. The nonvolatile semiconductor memory device according to claim 4, wherein

the electric capacitance of at least one of said first, second, third and fourth insulator films is different from the electric capacitances of remaining said insulator films.

7. The nonvolatile semiconductor memory device according to claim 4, further comprising a lower electrode for applying a potential to said second charge trap insulator film for trapping charges.

8. The nonvolatile semiconductor memory device according to claim 7, wherein

said lower electrode includes a polysilicon film or an impurity diffusion region.

9. The nonvolatile semiconductor memory device according to claim 4, having first charge trap regions trapping charges in a region including a portion corresponding to the boundary between said source region and said channel region and a region including a portion corresponding to the boundary between said drain region and said channel region in said first charge trap insulator film while having second charge trap regions trapping charges in a region including a portion corresponding to the boundary between said source region and said channel region and a region including a portion corresponding to the boundary between said drain region and said channel region in said second charge trap insulator film.

10. The nonvolatile semiconductor memory device according to claim 9, capable of storing information of four bits in one said memory cell.

11. The nonvolatile semiconductor memory device according to claim 1, wherein

said lower insulator film includes a charge trap insulator film capable of trapping charges.

12. The nonvolatile semiconductor memory device according to claim 11, wherein

said lower insulator film has a multilayer structure of a first insulator film, said charge trap insulator film and a second insulator film.

13. The nonvolatile semiconductor memory device according to claim 12, wherein

said charge trap insulator film is a nitride film.

14. The nonvolatile semiconductor memory device according to claim 12, further including a lower electrode applying a potential to said charge trap insulator film for trapping charges.

15. The nonvolatile semiconductor memory device according to claim 14, wherein

said lower electrode includes a polysilicon film or an impurity diffusion region.

16. The nonvolatile semiconductor memory device according to claim 12, including charge trap regions trapping charges in a region including a portion corresponding to the boundary between said source region and said channel region and a region including a portion corresponding to the boundary between said drain region and said channel region in said charge trap insulator film.