Circuits and methods for screening for defective memory cells in semiconductor memory devices

• US 20040008550A1
• Filed: 05/27/2003
• Published: 01/15/2004
• Est. Priority Date: 05/27/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kwang-Jin, Cho, Uk-Rae, Son, Young-Jae
• Granted Patent: US 6,901,014 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.

Claims

1. A semiconductor memory device comprising:

a power supply voltage;

a memory cell;

a first driver for supplying the power supply voltage to the memory cell in response to a cell power control signal; and

a second driver for supplying a voltage lower than the power supply voltage to the memory cell in response to a cell power down signal.

2. The device of claim 1, wherein the first driver is a PMOS transistor that is controlled by the cell power control signal.

3. The device of claim 1, wherein the second driver is a NMOS transistor that is controlled by the cell power down signal.

4. The device of claim 1, wherein the memory cell is a SRAM (static random access memory) cell.

5. The device of claim 1, further comprising a control circuit for generating the cell power control signal, the control circuit comprising:

a first test pad;

a second test pad;

a cell power control circuit for setting a cell power-off mode in response to an input from the second test pad;

a first gate circuit for receiving an output of the cell power control circuit and the input from the second pad; and

a second gate circuit for generating the cell power control signal in response to an output of the first gate circuit and an input from the first test pad.

6. The device of claim 5, wherein the cell power control circuit comprises a JTAG test circuit.

7. The device of claim 1, further comprising a control circuit for generating the cell power control signal and the cell power down signal, the control circuit comprising:

a first test pad;

a second test pad;

a cell power control circuit for setting a cell power-off mode in response to an input from the second test pad; and

a gate circuit for generating the cell power control signal in response to an output of the cell power control circuit and the input from the second test pad.

8. The device of claim 7, wherein the control circuit further comprises:

an external voltage pad; and

a voltage converter for converting a voltage supplied through the external voltage pad into the power supply voltage.

9. The device of claim 7, wherein the cell power control circuit comprises a JTAG test circuit.

10. A method of screening defective memory cells in a semiconductor memory device, comprising the steps of:

writing data into a memory cell, during a first period of time;

stopping a supply of a power supply voltage into the memory cell in response to a cell power control signal having a first logic state during a second period of time subsequent to the first period of time;

supplying the power supply voltage into the memory cell in response to the cell power control signal having a second logic state and reading data from the memory cell, during a third period of time subsequent to the second period of time; and

writing data into the memory cell after the cell power control signal transits to the first logic state to stop the supply of the power supply voltage to the cell and then reading data from the memory cell after the cell power control signal transits to the second logic state to enable the supply of the power supply signal to the cell, during a fourth period of time subsequent to the third period of time.

11. The method of claim 10, further comprising a step of generating the cell power control signal according to a test signal using a JTAG test circuit.

12. A semiconductor memory device comprising:

a power supply voltage;

a plurality of sub-memory blocks, each comprising a plurality of memory cells arranged in rows and columns;

a plurality of column decoders and bitline sense amplifiers associated with corresponding sub-memory blocks;

sub-row decoders disposed between the sub-memory blocks; and

drivers for supplying the power supply voltage to the memory cells in response to a cell power control signal.

13. The device of claim 12, comprising a plurality of memory blocks, each memory blocks comprising an arrangement of unit blocks, wherein each unit block comprises a two sub-memory blocks, a sub-row decoder, and two drivers, wherein each memory block is addressable by main row decoders.

14. The device of claim 13, wherein the cell power control signal is applied to a pre-decoder to activate the main row decoders, which controls a supply of the power supply voltage to the memory cells of the main memory cell blocks.

15. The device of claim 13, wherein the cell power control signal is applied to the sub-row decoders to control a supply of the power supply voltage to one or more unit blocks of one or more memory blocks.

16. The device of claim 12, wherein the drivers are disposed in conjunction areas between the sub-row decoder and the bitline sense amplifiers.

17. A semiconductor memory device comprising:

a power supply voltage;

a memory cell;

a first driver for supplying the power supply voltage to the memory cell in response to a cell power control signal; and

a control circuit for generating the cell power control signal in response to a test control signal.

18. The device of claim 17, wherein the test control signal specifies one of a package-level test mode and a wafer-level test mode.

19. The device of claim 17, wherein the control circuit comprises:

a first test pad;

a second test pad;

a cell power control circuit for setting a cell power-off mode in response to an input from the second test pad; and

a gate circuit for generating the cell power control signal in response to an output of the cell power control circuit and the input from the second test pad.