Handling node address failure in a distributed nodal system of processors

• US 20040010568A1
• Filed: 06/26/2002
• Published: 01/15/2004
• Est. Priority Date: 06/26/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Goodman, Brian Gerard, Jesionowski, Leonard George, Yardy, Raymond, Hill, Ronald Faye Jr.
• Granted Patent: US 7,092,990 B2
• Time in Patent Office: Days
• US Class Current: 709/220
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: H04L 61/5046 Resolving address allocation conflicts; Testing of addresses testing when self-assigning an address H04L61/5092
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06

Abstract

Addressing failure is handled in a nodal system of processor nodes, which comprise at least one processor and at least one interface to a network. Upon detection of a node address failure of a processor node for the network, such as lack of a node address, or presence of a duplicate address, the processor node is disabled from the network, thereby temporarily failing the processor node so that the system remains operational. An alternate node address stored in nonvolatile memory may be selected that avoids the node address failure.

Claims

1. A distributed nodal system of processors, comprising:

a network; and

a plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

at least one of said plurality of processor nodes;

upon detection of a node address failure of said processor node for said network, disables said processor node from said network at said at least one interface.

2. The distributed nodal system of processors of claim 1,

wherein said at least one processor node:

additionally comprises a nonvolatile memory;

maintains an alternate node address of said processor node in said nonvolatile memory;

detects said node address failure, by attempting to determine its own node address; and

failing to determine any usable node address as its own, selects said alternate node address in said nonvolatile memory.

3. The distributed nodal system of processors of claim 1, wherein said at least one processor node detects said node address failure, by sensing said network at said at least one interface.

4. A distributed nodal system of processors, comprising:

a network; and

a plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

at least one of said plurality of processor nodes;

determines a nominal node address as its own;

senses node addresses of other processor nodes of said network;

compares said sensed node addresses of other processor nodes with said nominal node address;

determines existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure of said processor node for said network; and

upon detection of said node address failure of said processor node for said network, disables said processor node nominal node address from said network at said at least one interface.

5. The distributed nodal system of processors of claim 4, wherein said at least one processor node:

upon detection of said node address failure of said processor node for said network, additionally selects a node address that avoids said node address failure, said selected node address for addressing said processor node in said network at said at least one interface upon enabling said processor node in said network.

6. The distributed nodal system of processors of claim 5, wherein said at least one processor node:

additionally comprises a nonvolatile memory;

maintains an alternate node address of said processor node in said nonvolatile memory;

upon said determination of a conflict and detection of said node address failure of said processor node for said network, further compares said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selects said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

7. A distributed nodal system of processors, comprising:

a network; and

a plurality of processor nodes comprising nodes of said network, at least two of said plurality of processor nodes subject to reset, and comprising at least one processor, at least one interface to said network, and a timer, said timer maintaining an indication of time since said processor node has been reset;

(I) at least one of said plurality of processor nodes;

determines a nominal node address as its own;

senses node addresses of other processor nodes of said network;

compares said sensed node addresses of other processor nodes with said nominal node address;

determines existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure in said network; and

(II) said processor node having said conflicting sensed node address;

compares the time of said timer of said processor node to the time of said timer of said other processor node having said conflicting said sensed node address, to determine the processor node having the more recent time of said timers; and

if said processor node has said more recent time,

disables said processor node nominal node address from said network at said at least one interface.

8. The distributed nodal system of processors of claim 7, wherein said processor node having said more recent time:

additionally selects a node address that avoids said node address failure, said selected node address for addressing said processor node having said more recent time, in said network, upon enabling said processor node in said network.

9. The distributed nodal system of processors of claim 8, wherein said processor node having said more recent time:

additionally comprises a nonvolatile memory;

maintains an alternate node address of said processor node in said nonvolatile memory;

further compares said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selects said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

10. A processor node for a distributed nodal system of processors, said system comprising a network and a plurality of processor nodes, said processor node comprising:

at least one interface to said network; and

at least one processor, said at least one processor;

upon detection of a node address failure of said processor node for said network, disables said processor node from said network at said at least one interface.

11. The processor node of claim 10, additionally comprising a nonvolatile memory;

and wherein said at least one processor;

maintains an alternate node address of said processor node in said nonvolatile memory;

detects said node address failure, by attempting to determine its own node address; and

upon failing to determine any usable node address as its own, selects said alternate node address in said nonvolatile memory.

12. The processor node of claim 10, wherein said at least one processor detects said node address failure, by sensing said network at said at least one interface.

13. A processor node for a distributed nodal system of processors, said system comprising a network and a plurality of processor nodes, said processor node comprising:

at least one interface to said network; and

at least one processor, said at least one processor;

determines a nominal node address as its own;

senses node addresses of other processor nodes of said network;

compares said sensed node addresses of other processor nodes with said nominal node address;

determines existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure of said processor node for said network; and

upon detection of said node address failure of said processor node for said network, disables said processor node nominal node address from said network at said at least one interface.

14. The processor node of claim 13, wherein said at least one processor:

upon detection of said node address failure of said processor node for said network, additionally selects a node address that avoids said node address failure, said selected node address for addressing said processor node in said network at said at least one interface upon enabling said processor node in said network.

15. The processor node of claim 14, additionally comprising a nonvolatile memory;

and

wherein said at least one processor;

maintains an alternate node address of said processor node in said nonvolatile memory;

upon said determination of a conflict and detection of said node address failure of said processor node for said network, further compares said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selects said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

16. A processor node for a distributed nodal system of processors, said system comprising a network and a plurality of processor nodes, at least two of said plurality of processor nodes subject to reset, said processor node comprising one of said plurality of processor nodes subject to reset:

at least one interface to said network;

a timer, said timer maintaining an indication of time since said processor node has been reset; and

at least one processor, said at least one processor;

determines a nominal node address as its own;

senses node addresses of other processor nodes of said network;

compares said sensed node addresses of other processor nodes with said nominal node address;

determines existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure in said network; and

compares the time of said timer of said processor node to the time of said timer of said other processor node having said conflicting said sensed node address, to determine the processor node having the more recent time of said timers; and

if said processor node has said more recent time, disables said processor node nominal node address from said network at said at least one interface.

17. The processor node of claim 16, wherein said at least one processor, upon said processor node having said more recent time:

additionally selects a node address that avoids said node address failure, said selected node address for addressing said processor node having said more recent time, in said network, upon enabling said processor node in said network.

18. The processor node of claim 17, additionally comprising a nonvolatile memory;

and

wherein said at least one processor maintains an alternate node address of said processor node in said nonvolatile memory; and

upon said processor node having said more recent time, further compares said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selects said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

19. An automated data storage library, comprising:

a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

at least one of said plurality of processor nodes;

upon detection of a node address failure of said processor node for said network, disables said processor node from said network at said at least one interface.

20. The automated data storage library of claim 19, wherein said at least one processor node:

additionally comprises a nonvolatile memory;

maintains an alternate node address of said processor node in said nonvolatile memory;

detects said node address failure, by attempting to determine its own node address; and

upon failing to determine any usable node address as its own, selects said alternate node address in said nonvolatile memory.

21. The automated data storage library of claim 19, wherein said at least one processor node detects said node address failure, by sensing said network at said processor node interface.

22. An automated data storage library, comprising:

a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

at least one of said plurality of processor nodes;

determines a nominal node address as its own;

senses node addresses of other processor nodes of said network;

compares said sensed node addresses of other processor nodes with said nominal node address;

determines existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure of said processor node for said network; and

upon detection of said node address failure of said processor node for said network, disables said processor node nominal node address from said network at said at least one interface.

23. The automated data storage library of claim 22, wherein said at least one processor node:

upon detection of said node address failure of said processor node for said network, additionally selects a node address that avoids said node address failure, said selected node address for addressing said processor node in said network at said at least one interface upon enabling said processor node in said network.

24. The automated data storage library of claim 23, wherein said at least one processor node:

additionally comprises a nonvolatile memory;

maintains an alternate node address of said processor node in said nonvolatile memory;

upon said determination of a conflict and detection of said node address failure of said processor node for said network, further compares said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selects said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

25. An automated data storage library, comprising:

a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, at least two of said plurality of processor nodes subject to reset, and comprising at least one processor, at least one interface to said network, and a timer, said timer maintaining an indication of time since said processor node has been reset;

(I) at least one of said plurality of processor nodes;

determines a nominal node address as its own;

senses node addresses of other processor nodes of said network;

compares said sensed node addresses of other processor nodes with said nominal node address;

determines existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure in said network; and

(II) said processor node having said conflicting sensed node address;

compares the time of said timer of said processor node to the time of said timer of said other processor node having said conflicting said sensed node address, to determine the processor node having the more recent time of said timers; and

if said processor node has said more recent time,

disables said processor node nominal node address from said network at said at least one interface.

26. The automated data storage library of claim 25, wherein said processor node having said more recent time:

additionally selects a node address that avoids said node address failure, said selected node address for addressing said processor node having said more recent time, in said network, upon enabling said processor node in said network.

27. The automated data storage library of claim 26, wherein said processor node having said more recent time:

additionally comprises a nonvolatile memory;

maintains an alternate node address of said processor node in said nonvolatile memory;

further compares said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selects said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

28. A method for handling addressing failure of a network of an automated data storage library, said automated data storage library for accessing data storage media, said automated data storage library comprising a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

said method comprising the steps of;

detecting a node address failure of one of said plurality of processor nodes for said network; and

upon detecting said node address failure, disabling said processor node having said node address failure from said network at said at least one interface.

29. The method of claim 28, wherein said at least one processor node additionally comprises a nonvolatile memory;

said method additionally comprising the steps of;

maintaining an alternate node address of said processor node in said nonvolatile memory;

detecting said node address failure, by attempting to determine a node address for said processor node; and

upon failing to determine any usable node address for said processor node, selecting said alternate node address in said nonvolatile memory for said processor node having said node address failure.

30. The method of claim 28, wherein said step of detecting said node address failure, comprises said at least one processor node sensing said network at said processor node interface.

31. A method for handling addressing failure of a network of an automated data storage library, said automated data storage library for accessing data storage media, said automated data storage library comprising a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

said method comprising the steps of;

determining a nominal node address of at least one of said plurality of processor nodes;

sensing node addresses of other processor nodes of said network;

comparing said sensed node addresses of other processor nodes with said nominal node address;

determining existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure of said processor node for said network; and

upon detection of said node address failure of said processor node for said network, disabling said processor node nominal node address having said node address failure from said network at said at least one interface.

32. The method of claim 31, additionally comprising the step of:

upon detection of said node address failure of said processor node for said network, selecting a node address that avoids said node address failure, said selected node address for addressing said processor node having said node address failure, in said network, upon enabling said processor node in said network.

33. The method of claim 32, wherein said at least one processor node additionally comprises a nonvolatile memory;

said method additionally comprising the steps of;

maintaining an alternate node address of said at least one processor node in said nonvolatile memory;

upon said determination of a conflict and detection of said node address failure of said at least one processor node for said network, further comparing said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selecting said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

34. A method for-handling addressing failure of a network of an automated data storage library, said automated data storage library for accessing data storage media, said automated data storage library comprising a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, at least two of said plurality of processor nodes subject to reset, and comprising at least one processor, at least one interface to said network, and a timer, said timer maintaining an indication of time since said processor node has been reset;

said method comprising the steps of;

determining a nominal node address of at least one of said plurality of processor nodes;

sensing node addresses of other processor nodes of said network;

comparing said sensed node addresses of other processor nodes with said nominal node address of said at least one processor node;

determining existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address of said at least one processor node, said existing conflict comprising a node address failure in said network;

comparing the time of said timer of said processor node having said nominal node address to the time of said timer of said other processor node having said conflicting said sensed node address, to determine the processor node having the more recent time of said timers; and

if said processor node having said nominal node address has said more recent time, disabling said processor node nominal node address from said network at said at least one interface.

35. The method of claim 34, additionally comprising the step of:

selecting a node address for said processor node having said more recent time, that avoids said node address failure, said selected node address for addressing said processor node having said more recent time, in said network, upon enabling said processor node in said network.

36. The method of claim 35, wherein said automated data storage library additionally comprises a nonvolatile memory;

and wherein said method additionally comprising the steps of;

maintaining an alternate node address in said nonvolatile memory;

further comparing said alternate node address of said nonvolatile memory for said processor node having said more recent time with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, selecting said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

37. A computer program product of a computer readable medium usable with a programmable computer, said computer program product having computer readable program code embodied therein for handling addressing failure of a nodal system of processors, said nodal system comprising a network;

and a plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

said computer program product comprising;

computer readable program code which causes said at least one processor of at least one of said processor nodes, to detect a node address failure of said processor node for said network; and

computer readable program code which causes said at least one processor of said processor node, to, upon detecting said node address failure, disable said processor node from said network at said at least one interface.

38. The computer program product of claim 37, wherein said processor node additionally comprises a nonvolatile memory;

and wherein said computer program product additionally comprises;

computer readable program code which causes said at least one processor of said processor node to maintain an alternate node address of said processor node in said nonvolatile memory;

said computer readable program code which causes said at least one processor of said processor node to detect said node address failure, comprises causing said at least one processor of said processor node to attempt to determine its own node address; and

said computer readable program code which causes said at least one processor of said processor node to, upon failing to determine any usable node address as its own, to select said alternate node address in said nonvolatile memory.

39. The computer program product of claim 37, wherein said computer readable program code which causes said at least one processor of said processor node to detect said node address failure, comprises causing said at least one processor of said processor node to sense said network at said processor node interface.

40. A computer program product of a computer readable medium usable with a programmable computer, said computer program product having computer readable program code embodied therein for handling addressing failure of a nodal system of processors, said nodal system comprising a network;

and a plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said network;

said computer program product comprising;

computer readable program code which causes said at least one processor of at least one of said processor nodes, to determine a nominal node address as its own;

computer readable program code which causes said at least one processor of said processor node, to sense node addresses of other processor nodes of said network;

computer readable program code which causes said at least one processor of said processor node, to compare said sensed node addresses of other processor nodes with said nominal node address;

computer readable program code which causes said at least one processor of said processor node, to determine existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address, said existing conflict comprising a node address failure of said processor node for said network; and

computer readable program code which causes said at least one processor of said processor node, to, upon detection of said node address failure of said processor node for said network, disable said processor node nominal node address from said network at said at least one interface.

41. The computer program product of claim 40, wherein said computer program product additionally comprises:

computer readable program code which causes said at least one processor of said processor node, to, upon detection of said node address failure of said processor node for said network, select a node address that avoids said node address failure, said selected node address for addressing said processor node in said network upon enabling said processor node in said network.

42. The computer program product of claim 41, wherein said processor node additionally comprises a nonvolatile memory;

and said computer program product;

additionally comprises computer readable program code which causes said at least one processor of said processor node, to maintain an alternate node address of said processor node in said nonvolatile memory;

said computer readable program code which causes said at least one processor of said processor node to select a node address that avoids said node address failure, comprises causing said at least one processor of said processor node;

to compare said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, to select said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

43. A computer program product of a computer readable medium usable with a programmable computer, said computer program product having computer readable program code embodied therein for for handling addressing failure of a nodal system of processors, said nodal system comprising a network;

and a plurality of processor nodes comprising nodes of said network, at least two of said plurality of processor nodes subject to reset, and comprising at least one processor, at least one interface to said network, and a timer, said timer maintaining an indication of time since said processor node has been reset;

said computer program product comprising;

computer readable program code which causes said at least one processor of at least one of said processor nodes, to determine a nominal node address of said processor node;

computer readable program code which causes said at least one processor of said processor node, to sense node addresses of other processor nodes of said network;

computer readable program code which causes said at least one processor of said processor node, to compare said sensed node addresses of other processor nodes with said nominal node address of said processor node;

computer readable program code which causes said at least one processor of said processor node, to determine existence of any conflict between at least one of said sensed node addresses of other processor nodes with said nominal node address of said processor node, said existing conflict comprising a node address failure in said network;

computer readable program code which causes said at least one processor of said processor node, to compare the time of said timer of said processor node having said nominal node address to the time of said timer of said other processor node having said conflicting said sensed node address, to determine the-processor node having the more recent time of said timers; and

computer readable program code which causes said at least one processor of said processor node, to, if said processor node is determined to have said more recent time of said timers, disable said processor node nominal node address from said network at said at least one interface.

44. The computer program product of claim 43, wherein said computer program product additionally comprises:

computer readable program code which causes said at least one processor of said processor node, to, if said processor node is determined to have said more recent time of said timers, select a node address that avoids said node address failure, said selected node address for addressing said processor node in said network upon enabling said processor node in said network.

45. The computer program product of claim 44, wherein said processor node additionally comprises a nonvolatile memory;

and

said computer program product;

additionally comprises computer readable program code which causes said at least one processor of said processor node, to maintain an alternate node address of said processor node in said nonvolatile memory;

said computer readable program code which causes said at least one processor of said processor node having said more recent time to select a node address that avoids said node address failure, comprises causing said at least one processor of said processor node;

to further compare said alternate node address of said nonvolatile memory with said sensed node addresses of said other processor nodes; and

if said alternate node address avoids conflict with said sensed node addresses of said other processor nodes, to select said node address that avoids said node address failure, by selecting said alternate node address of said nonvolatile memory.

46. An automated data storage library, comprising:

a plurality of storage shelves for storing data storage media;

at least one data storage drive for reading and/or writing data with respect to said data storage media;

at least one robot accessor for transporting said data storage media between said plurality of storage shelves and said at least one data storage drive;

a network; and

a plurality of processor nodes for operating said automated data storage library, said plurality of processor nodes comprising nodes of said network, each of said plurality of processor nodes comprising at least one processor and at least one interface to said-network;

at least one of said plurality of processor nodes associated with at least one element of said library, said processor node;

maintains designating information of said at least one element associated with said processor node;

determines a nominal node address as its own for said network;

senses present designating information of at least one element associated with said processor node;

compares said present designating information to said maintained designating information;

determines whether a-match is made between said compared said present designating information and said maintained designating information, a failure of said match comprising a node address failure of said processor node for said network; and

upon said node address failure of said processor node for said network, disables said processor node nominal node address from said network at said at least one interface.

47. A processor node for a distributed nodal system of processors, said system comprising a network and a plurality of processor nodes, said processor node associated with at least one element, said processor node comprising:

at least one interface to said network; and

at least one processor, said at least one processor;

maintains designating information of said at least one element associated with said processor node;

determines a nominal node address as an address for said processor node for said network;

senses present designating information of at least one element associated with said processor node;

compares said present designating information to said maintained designating information;

determines whether a match is made between said compared said present designating information and said maintained designating information, a failure of said match comprising a node address failure of said processor node for said network; and

upon said node address failure of said processor node for said network, disables said processor node nominal node address from said network at said at least one interface.

48. A method for determining and handling addressing failure of a processor node of a distributed nodal system of processors, said system comprising a network and a plurality of processor nodes, at least one of said plurality of processor nodes associated with at least one element, said at least one processor node comprising at least one processor and at least one interface to said network;

said method comprising the steps of;

maintaining designating information of said at least one element associated with said processor node;

determining a nominal node address as an address for said processor node for said network;

sensing present designating information of at least one element associated with said processor node;

comparing said present designating information to said maintained designating information;

determining whether a match is made between said compared said present designating information and said maintained designating information, a failure of said match comprising a node address failure of said processor node for said network; and

upon said node address failure of said processor node for said network, disabling said processor node nominal node address from said network at said at least one interface.

49. A computer program product of a computer readable medium usable with a programmable computer, said computer program product having computer readable program code embodied therein for determining and handling addressing failure of a nodal system of processors, said nodal system comprising a network;

and a plurality of processor nodes comprising nodes of said network, at least one of said plurality of processor nodes associated with at least one element, said at least one processor node comprising at least one processor and at least one interface to said network;

said computer program product comprising;

computer readable program code which causes said at least one processor of said processor node to maintain designating information of said at least one element associated with said processor node;

computer readable program code which causes said at least one processor of said processor node to determine a nominal node address as an address for said processor node for said network;

computer readable program code which causes said at least one processor of said processor node to sense present designating information of at least one element associated with said processor node;

computer readable program code which causes said at least one processor of said processor node to compare said present designating information to said maintained designating information;

computer readable program code which causes said at least one processor of said processor node to determine whether a match is made between said compared said present designating information and said maintained designating information, a failure of said match comprising a node address failure of said processor node for said network; and

computer readable program code which causes said at least one processor of said processor node to, upon said node address failure of said processor node for said network, disable said processor node nominal node address from said network at said at least one interface.