Uniform interface for a functional node in an adaptive computing engine

• US 20040010645A1
• Filed: 05/21/2003
• Published: 01/15/2004
• Est. Priority Date: 06/25/2002
• Status: Active Grant

• Current Assignee: QST Holdings LLC
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Scheuermann, W. James, Hogenauer, Eugene B.
• Granted Patent: US 7,225,279 B2
• Time in Patent Office: Days
• US Class Current: 710/107
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A computational unit, or node, in an adaptive computing engine uses a uniform interface to a network to communicate with other nodes and resources. The uniform interface is referred to as a “node wrapper.” The node wrapper includes a hardware task manager (HTM), a data distributor, optional direct memory access (DMA) engine and a data aggregator. The hardware task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The HTM coordinates a nodes assigned tasks using a task lists. A “ready-to-run queue” is implemented as a first-in first-out stack. The HTM uses a top-level finite-state machine (FSM) that communicates with a number of subordinate FSMs to control individual HTM components. The Data Distributor interfaces between the node'"'"'s input pipeline register and various memories and registers within the node. Different types of data distribution are possible based upon the values in service and auxiliary fields of a 50-bit control structure. The Data Aggregator arbitrates among up to four node elements that request access to the node'"'"'s output pipeline register for the purpose of transferring data to the intended destination via the network. The DMA Engine uses a five-register model. The registers include a Starting Address Register, an Address Stride Register, a Transfer Count Register, a Duty Cycle Register, and a Control Register including a GO bit, Target Node number/port number, and DONE protocol. A control node, or “K-node,” is used to control various aspects of the HTM, data distributor, data aggregator and DMA operations within the nodes of the system.

Claims

1. A data distributor in a computational unit, wherein the data distributor receives data from a network in an adaptive computing engine and distributes the data to components within the computational unit, the data distributor comprising

an input mechanism for receiving the data;

a distribution mechanism responsive to a control signal for distributing the data to a selected component; and

a control mechanism responsive to a control signal for distributing the data to the selected component in a selected manner.

2. The data distributor of claim 1, wherein a selected component includes a register.

3. The data distributor of claim 1, wherein a selected component includes a memory.

4. The data distributor of claim 1, wherein a selected manner of distributing the data includes a look-up table.

5. The data distributor of claim 4, wherein a selected manner of distributing the data includes using an output port number to distribute the data.

6. The data distributor of claim 4, wherein a selected manner of distributing the data includes using a direct-memory address transfer to distribute the data.

7. The data distributor of claim 4, wherein a selected manner of distributing the data includes using an interrupt to distribute the data.

8. The data distributor of claim 1, wherein the input mechanism includes a pipeline register.

9. A data aggregator in a computational unit in an adaptive computing engine is used to aggregate 4data for transfer from the computational unit to the network, wherein the computational unit includes multiple components, wherein each component can request transfer of data to the network, the data aggregator comprising

an output register coupled to the network;

and

an arbiter mechanism for arbitrating priority of the requests from the multiple components.

10. The data aggregator of claim 9, wherein one of the multiple components includes a Peek/Poke Module.

11. The data aggregator of claim 9, wherein one of the multiple components includes a Execution Unit.

12. The data aggregator of claim 9, wherein one of the multiple components includes a DMA Engine.

13. The data aggregator of claim 9, wherein one of the multiple components includes a HTM Message Generator.

14. A method for distributing data in a computational unit, the method comprising

receiving data from a network in an adaptive computing engine;

distributing the data to components within the computational unit according to a control signal for distributing the data to a selected component and according to a control signal for distributing the data to the selected component in a selected manner.

15. The method of claim 14, wherein a selected component includes a register.

16. The method of claim 14, wherein a selected component includes a memory.

17. The method of claim 14, wherein a selected manner of distributing the data includes using a look-up table.

18. The method of claim 17, wherein a selected manner of distributing the data includes using an output port number to distribute the data.

19. The method of claim 17, wherein a selected manner of distributing the data includes using a direct-memory address transfer to distribute the data.

20. The method of claim 17, wherein a selected manner of distributing the data includes using an interrupt to distribute the data.

21. The data distributor of claim 14, wherein the input mechanism includes a pipeline register.

22. A method for outputting data to a network from a computational unit in an adaptive computing engine, the method comprising

arbitrating among multiple components to select a component'"'"'s output data to transfer to the network.

23. The method of claim 22, further comprising

sending data to an output register coupled to the network;

and

prioritizing the requests from the multiple components.

24. The method of claim 22, wherein one of the multiple components includes a Peek/Poke Module.

25. The data aggregator of claim 22, wherein one of the multiple components includes a Execution Unit.

26. The data aggregator of claim 22, wherein one of the multiple components includes a DMA Engine.

27. The data aggregator of claim 22, wherein one of the multiple components includes a HTM Message Generator.