Stable PD-SOI devices and methods

• US 20040014304A1
• Filed: 07/18/2002
• Published: 01/22/2004
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 6,828,632 B2
• Time in Patent Office: Days
• US Class Current: 438/570
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/806 with Schottky drain or source contact

Abstract

One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer, and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.

Claims

1. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed above the oxide insulation layer, including;

a first silicon (Si) epitaxial layer disposed above the oxide insulation layer, the first Si epitaxial layer including a number of recombination centers;

a silicon germanium (Si—

Ge) epitaxial layer disposed above the first Si epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers; and

a second Si epitaxial layer disposed above the Si—

Ge epitaxial layer;

at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—

Ge epitaxial layer including recombination centers in the source region and the drain region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;

a gate formed above the gate oxide layer;

a metal silicide layer formed above the second Si epitaxial layer; and

a lateral metal Schottky layer selectively formed above the second Si epitaxial layer to contact the source region and the active region.

2. The structure of claim 1, wherein the recombination centers include voids formed in the structure.

3. The structure of claim 1, wherein the recombination centers include helium-implanted nanocavities formed in the structure.

4. The structure of claim 1, wherein the lateral metal Schottky layer includes tungsten (W).

5. The structure of claim 1, wherein the lateral metal Schottky layer includes Nickel (Ni).

6. The structure of claim 1, wherein the lateral metal Schottky layer includes titanium (Ti).

7. The structure of claim 1, wherein the lateral metal Schottky layer includes gold (Au).

8. The structure of claim 1, wherein the lateral metal Schottky layer includes cobalt (Co).

9. The structure of claim 1, wherein the lateral metal Schottky layer includes magnesium (Mg).

10. The structure of claim 1, wherein the metal silicide layer includes tungsten (W) silicide.

11. The structure of claim 1, wherein the metal silicide layer includes cobalt (Co) silicide.

12. The structure of claim 1, wherein the metal silicide layer includes Nickel (Ni) silicide.

13. The structure of claim 1, wherein the metal silicide layer and the lateral metal Schottky layer provide a parallel connection between the source region and the active region.

14. The structure of claim 1, wherein the structure forms an NFET-SOI device, and both the first Si epitaxial layer and the second Si epitaxial layer include p−

type silicon.

15. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—

Ge) epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers;

at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—

Ge epitaxial layer including recombination centers in the source region and the drain region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region; and

a gate formed above the gate oxide layer.

16. The structure of claim 15, wherein the recombination centers include voids formed in the Si—

Ge epitaxial layer.

17. The structure of claim 15, wherein the recombination centers include helium-implanted nanocavities formed in the Si—

Ge epitaxial layer.

18. The structure of claim 15, wherein the active region includes a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer.

19. The structure of claim 15, further comprising a lateral metal Schottky layer selectively formed above the active region to contact the source region and the active region.

20. The structure of claim 15, wherein the active region includes p−

type silicon and both the source region and the drain region include n−

type silicon to form an NFET-SOI device.

21. The structure of claim 15, wherein the active region includes n−

type silicon and both the source region and the drain region include p−

type silicon to form an PFET-SOI device.

22. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed above the oxide insulation layer, including a number of recombination centers positioned near the oxide insulator layer;

at least one source region and at least one drain region formed in the active region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;

a gate formed above the gate oxide layer; and

a lateral metal Schottky layer selectively formed to contact the source region and the active region.

23. The structure of claim 22, wherein the recombination centers include voids formed in the active region.

24. The structure of claim 22, wherein the recombination centers include helium-implanted nanocavities formed in the active region.

25. The structure of claim 22, further comprising a metal silicide layer formed above the active region to contact the source region and the active region in parallel with the lateral metal Schottky layer.

26. The structure of claim 22, wherein the active region includes p−

type silicon and both the source region and the drain region include n−

type silicon to form an NFET-SOI device.

27. The structure of claim 22, wherein the active region includes a multilayer epitaxy, including an Si—

Ge epitaxial layer.

28. The structure of claim 27, wherein the Si—

Ge epitaxial layer includes recombination centers, wherein the recombination centers include recombination centers in the source region and the drain region.

29. The structure of claim 22, wherein the lateral metal Schottky layer includes tungsten (W).

30. The structure of claim 22, wherein the lateral metal Schottky layer includes Nickel (Ni).

31. The structure of claim 22, wherein the lateral metal Schottky layer includes titanium (Ti).

32. The structure of claim 22, wherein the lateral metal Schottky layer includes gold (Au).

33. The structure of claim 22, wherein the lateral metal Schottky layer includes cobalt (Co).

34. The structure of claim 22, wherein the lateral metal Schottky layer includes magnesium (Mg).

35. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—

Ge) epitaxial layer;

at least one source region and at least one drain region formed in the active region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;

a gate formed above the gate oxide layer; and

a lateral metal Schottky layer selectively formed to contact the source region and the active region.

36. The structure of claim 35, wherein the Si—

Ge epitaxial layer includes a number of recombination centers in the source region and the drain region.

37. The structure of claim 35, wherein the active region includes a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer.

38. The structure of claim 35, further comprising a metal silicide layer formed above the active region to contact the source region and the active region in parallel with the lateral metal Schottky layer.

39. The structure of claim 35, wherein the active region includes p−

type silicon and both the source region and the drain region include n−

type silicon to form an NFET-SOI device.

40. The structure of claim 35, wherein the active region includes n−

type silicon and both the source region and the drain region include p−

type silicon to form an PFET-SOI device.

41. The structure of claim 35, wherein the lateral metal Schottky layer includes tungsten (W).

42. The structure of claim 35, wherein the lateral metal Schottky layer includes Nickel (Ni).

43. The structure of claim 35, wherein the lateral metal Schottky layer includes titanium (Ti).

44. The structure of claim 35, wherein the lateral metal Schottky layer includes gold (Au).

45. The structure of claim 35, wherein the lateral metal Schottky layer includes cobalt (Co).

46. The structure of claim 35, wherein the lateral metal Schottky layer includes magnesium (Mg).

47. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—

Ge) epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers;

at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—

Ge epitaxial layer including recombination centers in the source region and the drain region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region;

a gate formed above the gate oxide layer; and

a lateral metal Schottky layer selectively formed to contact the source region and the active region.

48. The structure of claim 47, wherein the recombination centers include voids formed in the Si—

Ge epitaxial layer.

49. The structure of claim 47, wherein the recombination centers include helium-implanted nanocavities formed in the Si—

Ge epitaxial layer.

50. The structure of claim 47, wherein the active region includes a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer.

51. The structure of claim 47, further comprising a metal silicide layer formed above the active region to contact the source region and the active region in parallel with the lateral metal Schottky layer.

52. The structure of claim 47, wherein the active region includes p−

type silicon and both the source region and the drain region include n−

type silicon to form an NFET-SOI device.

53. The structure of claim 47, wherein the lateral metal Schottky layer includes tungsten (W).

54. The structure of claim 47, wherein the lateral metal Schottky layer includes Nickel (Ni).

55. The structure of claim 47, wherein the lateral metal Schottky layer includes titanium (Ti).

56. The structure of claim 47, wherein the lateral metal Schottky layer includes gold (Au).

57. The structure of claim 47, wherein the lateral metal Schottky layer includes cobalt (Co).

58. The structure of claim 47, wherein the lateral metal Schottky layer includes magnesium (Mg).

59. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed above the oxide insulation layer, the active region including a silicon germanium (Si—

Ge) epitaxial layer, the active region including a number of recombination centers between the Si—

Ge epitaxial and the oxide insulation layer;

at least one source region and at least one drain region formed in the active region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region; and

a gate formed above the gate oxide layer.

60. The structure of claim 59, wherein the recombination centers include voids formed in the active region.

61. The structure of claim 59, wherein the recombination centers include helium-implanted nanocavities formed in the active region.

62. The structure of claim 59, wherein the Si—

Ge epitaxial layer includes a number of recombination centers in the source region and the drain region.

63. The structure of claim 59, wherein the active region includes p−

type silicon and both the source region and the drain region include n−

type silicon to form an NFET-SOI device.

64. The structure of claim 59, wherein the active region includes n−

type silicon and both the source region and the drain region include p−

type silicon to form an PFET-SOI device.

65. The structure of claim 59, further comprising a metal silicide layer formed above the active region to contact the source region and the active region.

66. The structure of claim 59, further comprising a lateral metal Schottky layer selectively formed to contact the source region and the active region.

67. The structure of claim 59, further comprising a metal silicide layer and a lateral metal Schottky layer selectively formed to contact the source region and the active region, wherein the metal silicide layer and the lateral metal Schottky layer provide a parallel contact between the source region and the active region.

68. A partially depleted silicon-on-insulator structure, comprising:

a substrate;

an oxide insulation layer disposed above the silicon substrate;

an active region formed on the oxide insulation layer, the active region including a silicon germanium (Si—

Ge) epitaxial layer, the active region including a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer, the Si—

Ge epitaxial layer including a number of recombination centers;

at least one source region and at least one drain region formed in the active region, the recombination centers in the Si—

Ge epitaxial layer including recombination centers in the source region and the drain region;

a gate oxide layer formed above the active region to define a channel region in the active region between the source region and the drain region; and

a gate formed above the gate oxide layer.

69. The structure of claim 68, wherein the recombination centers include voids formed in the structure.

70. The structure of claim 68, wherein the recombination centers include helium-implanted nanocavities formed in the structure.

71. The structure of claim 68, wherein the active region includes p−

type silicon and both the source region and the drain region include n−

type silicon to form an NFET-SOI device.

72. The structure of claim 68, wherein the active region includes n−

type silicon and both the source region and the drain region include p−

type silicon to form an PFET-SOI device.

73. The structure of claim 68, further comprising a metal silicide layer formed above the active region to contact the source region and the active region.

74. The structure of claim 68, further comprising a lateral metal Schottky layer selectively formed to contact the source region and the active region.

75. The structure of claim 68, further comprising a metal silicide layer and a lateral metal Schottky layer selectively formed to contact the source region and the active region, wherein the metal silicide layer and the lateral metal Schottky layer provide a parallel contact between the source region and the active region.

76. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:

forming a multilayer epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—

Ge) epitaxial layer;

providing shallow trench isolation (STI) in the multilayer epitaxy to form an SOI active region;

forming recombination centers in the multilayer epitaxy near the oxide insulating layer below the Si—

Ge epitaxial layer;

forming a number of wells in the multilayer epitaxy;

performing processing steps for forming active devices in the multilayer epitaxy;

forming recombination centers in the Si—

Ge epitaxial layer;

forming source/drain regions for the active devices;

forming a metal silicide over the active region of the active devices; and

forming a lateral Schottky on the metal silicide to contact a source region and the SOI active region.

77. The method of claim 76, further comprising:

forming contacts;

forming interconnects; and

performing back-end-of-line (BEOL) processes.

78. The method of claim 76, wherein forming a multilayer epitaxy on an oxide insulating layer includes:

forming a first silicon (Si) epitaxial layer on the oxide insulating layer;

forming the Si—

Ge epitaxial layer on the first Si epitaxial layer; and

forming a second silicon (Si) epitaxial layer on the Si—

Ge epitaxial layer.

79. The method of claim 76, wherein forming recombination centers in the multilayer epitaxy near the oxide insulating layer includes:

ion implanting helium in a Si epitaxial layer that is formed on the oxide insulating layer; and

annealing the Si epitaxial layer.

80. The method of claim 76, wherein, for each of the active devices, performing processing steps for forming active devices in the multilayer epitaxy includes:

ion implanting a channel in the multilayer epitaxy for the active device;

forming the gate for the active device on the channel; and

forming a spacer around the gate for the active device.

81. The method of claim 76, wherein forming recombination centers in the Si—

Ge epitaxial layer and forming source/drain regions for the active devices include;

implanting source/drain impurities in source/drain regions for the active devices;

ion implanting helium in the Sig-Ge epitaxial layer such that the recombination centers in the Si—

Ge epitaxial layer are formed in the source/drain regions; and

annealing the Si—

Ge epitaxial layer and the source/drain regions.

82. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes:

applying a Schottky mask; and

selectively deposit a metal using the mask to form the lateral Schottky.

83. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes selectively depositing tungsten (W).

84. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes selectively depositing nickel (Ni).

85. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes selectively depositing titanium (Ti).

86. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes selectively depositing gold (Au).

87. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes selectively depositing cobalt (Co).

88. The method of claim 76, wherein forming a lateral Schottky on the metal silicide includes selectively depositing magnesium (Mg).

89. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:

forming a multilayer epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—

Ge) epitaxial layer;

providing shallow trench isolation (STI) in the multilayer epitaxy to form an SOI active region;

forming a number of wells in the multilayer epitaxy;

performing processing steps for forming active devices in the multilayer epitaxy, each of the active devices being formed with a gate;

forming recombination centers in the Si—

Ge epitaxial layer; and

forming source/drain regions for the active devices.

90. The method of claim 89, wherein forming recombination centers in the Si—

Ge epitaxial layer and forming source/drain regions for the active devices include;

implanting source/drain impurities in source/drain regions for the active devices;

ion implanting helium in the Sig-Ge epitaxial layer such that the recombination centers in the Si—

Ge epitaxial layer are formed in the source/drain regions; and

annealing the Si—

Ge epitaxial layer and the source/drain regions.

91. The method of claim 89, further comprising forming recombination centers in the multilayer epitaxy near the oxide insulating layer below the Si—

Ge epitaxial layer.

92. The method of claim 89, further comprising forming a metal silicide over the active region of the active devices.

93. The method of claim 89, further comprising forming a lateral Schottky to contact a source region and the SOI active region.

94. The method of claim 89, further comprising:

forming a metal silicide over the active region of the active devices to contact a source region and the active region; and

forming a lateral Schottky on the metal silicide to contact the source region and the SOI active region in parallel with the metal silicide.

95. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:

forming a body layer on an oxide insulating layer;

providing shallow trench isolation (STI) in the body layer to form an SOI active region;

forming recombination centers in the body layer near the oxide insulating layer;

forming a number of wells in the body layer;

performing processing steps for forming active devices in the body layer, each of the active devices being formed with a gate;

forming source/drain regions for the active devices;

forming a metal silicide over the gates of the active devices; and

forming a lateral Schottky on the metal silicide.

96. The method of claim 95, wherein forming a body layer on an oxide insulating layer includes forming a multilayer epitaxy, including a silicon germanium (Si—

Ge) epitaxial layer.

97. The method of claim 96, forming a body layer on an oxide insulating layer further includes forming recombination centers in the Si—

GE epitaxial layer.

98. The method of claim 95, wherein forming recombination centers in the multilayer epitaxy near the oxide insulating layer includes:

ion implanting helium in a Si epitaxial layer that is formed on the oxide insulating layer; and

annealing the Si epitaxial layer.

99. The method of claim 95, wherein forming a lateral Schottky on the metal silicide includes selectively depositing tungsten (W).

100. The method of claim 95, wherein forming a lateral Schottky on the metal silicide includes selectively depositing nickel (Ni).

101. The method of claim 95, wherein forming a lateral Schottky on the metal silicide includes selectively depositing titanium (Ti).

102. The method of claim 95, wherein forming a lateral Schottky on the metal silicide includes selectively depositing gold (Au).

103. The method of claim 95, wherein forming a lateral Schottky on the metal silicide includes selectively depositing cobalt (Co).

104. The method of claim 95, wherein forming a lateral Schottky on the metal silicide includes selectively depositing magnesium (Mg).

105. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:

forming an epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—

Ge) epitaxial layer;

providing shallow trench isolation (STI) in the epitaxy to form an SOI active region;

forming a number of wells in the epitaxy;

performing processing steps for forming active devices in the epitaxy, each of the active devices being formed with a gate;

forming source/drain regions for the active devices;

forming a metal silicide over the gates of the active devices; and

forming a lateral Schottky on the metal silicide.

106. The method of claim 105, further comprising forming recombination centers in the epitaxy near the oxide insulating layer below the Si—

Ge epitaxial layer.

107. The method of claim 105, wherein forming a epitaxy on an oxide insulating layer further includes forming recombination centers in the Si—

GE epitaxial layer.

108. The method of claim 105, wherein forming a lateral Schottky on the metal silicide includes selectively depositing tungsten (W).

109. The method of claim 105, wherein forming a lateral Schottky on the metal silicide includes selectively depositing nickel (Ni).

110. The method of claim 105, wherein forming a lateral Schottky on the metal silicide includes selectively depositing titanium (Ti).

111. The method of claim 105, wherein forming a lateral Schottky on the metal silicide includes selectively depositing gold (Au).

112. The method of claim 105, wherein forming a lateral Schottky on the metal silicide includes selectively depositing cobalt (Co).

113. The method of claim 105, wherein forming a lateral Schottky on the metal silicide includes selectively depositing magnesium (Mg).

114. The method of claim 105, wherein forming a Si—

Ge epitaxial layer includes forming a relaxed Si—

Ge layer for a silicon-germanium-on-insulator (SGOI) device.

115. The method of claim 105, wherein forming an epitaxy includes forming a layer of strain-silicon on the Si—

Ge epitaxial layer to enhance carrier mobility in a channel region of a device.

116. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:

forming an epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—

Ge) epitaxial layer;

providing shallow trench isolation (STI) in the epitaxy to form an SOI active region;

forming a number of wells in the epitaxy;

performing processing steps for forming active devices in the epitaxy, each of the active devices being formed with a gate;

forming recombination centers in the Si—

Ge epitaxial layer;

forming source/drain regions for the active devices;

forming a metal silicide over the gates of the active devices; and

forming a lateral Schottky on the metal silicide.

117. The method of claim 116, further comprising forming recombination centers in the epitaxy near the oxide insulating layer below the Si—

Ge epitaxial layer.

118. The method of claim 116, wherein forming recombination centers in the Si—

Ge epitaxial layer and forming source/drain regions for the active devices include;

implanting source/drain impurities in source/drain regions for the active devices;

ion implanting helium in the Sig-Ge epitaxial layer such that the recombination centers in the Si—

Ge epitaxial layer are formed in the source/drain regions; and

annealing the Si—

Ge epitaxial layer and the source/drain regions.

119. The method of claim 116, wherein forming a lateral Schottky on the metal silicide includes selectively depositing tungsten (W).

120. The method of claim 116, wherein forming a lateral Schottky on the metal silicide includes selectively depositing nickel (Ni).

121. The method of claim 116, wherein forming a lateral Schottky on the metal silicide includes selectively depositing titanium (Ti).

122. The method of claim 116, wherein forming a lateral Schottky on the metal silicide includes selectively depositing gold (Au).

123. The method of claim 116, wherein forming a lateral Schottky on the metal silicide includes selectively depositing cobalt (Co).

124. The method of claim 116, wherein forming a lateral Schottky on the metal silicide includes selectively depositing magnesium (Mg).

125. The method of claim 116, wherein forming a Si—

Ge epitaxial layer includes forming a relaxed Si—

Ge layer for a silicon-germanium-on-insulator (SGOI) device.

126. The method of claim 116, wherein forming an epitaxy includes forming a layer of strain-silicon on the Si—

Ge epitaxial layer to enhance carrier mobility in a channel region of a device.

127. A method of fabricating a silicon-on-insulator (SOI) structure, comprising:

forming a multilayer epitaxy on an oxide insulating layer, including forming a silicon germanium (Si—

Ge) epitaxial layer;

providing shallow trench isolation (STI) in the multilayer epitaxy to form an SOI active region;

forming recombination centers in the multilayer epitaxy below the Si—

Ge epitaxial layer near the oxide insulating layer;

forming a number of wells in the multilayer epitaxy;

performing processing steps for forming active devices in the multilayer epitaxy, each of the active devices being formed with a gate;

forming recombination centers in the Si—

Ge epitaxial layer; and

forming source/drain regions for the active devices.

128. The method of claim 127, wherein forming recombination centers in the multilayer epitaxy near the oxide insulating layer includes:

ion implanting helium in a Si epitaxial layer that is formed on the oxide insulating layer; and

annealing the Si epitaxial layer.

129. The method of claim 127, wherein forming recombination centers in the Si—

Ge epitaxial layer and forming source/drain regions for the active devices include;

implanting source/drain impurities in source/drain regions for the active devices;

ion implanting helium in the Sig-Ge epitaxial layer such that the recombination centers in the Si—

Ge epitaxial layer are formed in the source/drain regions; and

annealing the Si—

Ge epitaxial layer and the source/drain regions.

130. The method of claim 127, further comprising forming a metal silicide over the active region of the active devices.

131. The method of claim 127, further comprising forming a lateral Schottky to contact a source region and the SOI active region.

132. The method of claim 127, further comprising:

forming a metal silicide over the active region of the active devices to contact a source region and the active region; and

forming a lateral Schottky on the metal silicide to contact the source region and the SOI active region in parallel with the metal silicide.

133. A semiconductor chip, comprising:

a silicon substrate;

an oxide insulation layer disposed above the silicon substrate;

an n−

type body layer disposed above a second portion of the oxide insulation layer, the n−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer;

a PFET device in association with the n−

type body layer, the PFET device including a source region and a silicided lateral Schottky layer in contact with the source region and the n−

type body layer;

a p−

type body layer disposed above a first portion of the oxide insulation layer, the p−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer; and

an NFET device in association with the p−

type body layer, the NFET device including a source region and both a silicide metal layer and a metal lateral Schottky layer in contact with the source region and the p−

type body layer.

134. The semiconductor chip of claim 133, wherein the Si—

Ge epitaxial layer in both the n−

type body layer and the p−

type body layer includes a number of recombination centers.

135. The semiconductor chip of claim 134, wherein the number of recombination centers includes a number of helium implanted nanocavities.

136. The semiconductor chip of claim 133, wherein both the n−

type body layer and the p−

type body layer include a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer.

137. The semiconductor chip of claim 136, wherein the number of recombination centers includes a number of helium implanted nanocavities.

138. The semiconductor chip of claim 133, wherein the Si—

Ge epitaxial layer in both the n−

type body layer and the p−

type body layer includes a number of recombination centers, and both the n−

type body layer and the p−

type body layer include a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer.

139. A semiconductor chip, comprising:

a silicon substrate;

an oxide insulation layer disposed above the silicon substrate;

an n−

type body layer disposed above a second portion of the oxide insulation layer, the n−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers, the n−

type body layer including a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer;

a PFET device in association with the n−

type body layer;

a p−

type body layer disposed above a first portion of the oxide insulation layer, the p−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers, the p−

type body layer including a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer; and

an NFET device in association with the p−

type body layer.

140. The semiconductor chip of claim 139, wherein:

the PFET device includes a source region and a silicided lateral Schottky layer in contact with the source region and the n−

type body layer; and

the NFET device includes a source region and both a silicided lateral Schottky layer and a metal lateral Schottky layer in contact with the source region and the p−

type body layer.

141. The semiconductor chip of claim 139, wherein the number of recombination centers includes a number of helium implanted nanocavities.

142. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein at least one of the processor and the memory device includes a semiconductor chip, comprising;

a silicon substrate;

an oxide insulation layer disposed above the silicon substrate;

an n−

type body layer disposed above a second portion of the oxide insulation layer, the n−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer;

a PFET device in association with the n−

type body layer, the PFET device including a source region and a silicided lateral Schottky layer in contact with the source region and the −

type body layer;

a p−

type body layer disposed above a first portion of the oxide insulation layer, the p−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer; and

an NFET device in association with the p−

type body layer, the NFET device including a source region and a metal lateral Schottky layer in contact with the source region and the p−

type body layer.

143. The system of claim 142, wherein the Si—

Ge epitaxial layer in both the n−

type body layer and the p−

type body layer includes a number of recombination centers.

144. The system of claim 142, wherein both the n−

type body layer and the p−

type body layer include a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer.

145. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein at least one of the processor and the memory device includes a semiconductor chip, comprising;

a silicon substrate;

an oxide insulation layer disposed above the silicon substrate;

an n−

type body layer disposed above a second portion of the oxide insulation layer, the n−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers, the n−

type body layer including a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer;

a PFET device in association with the n−

type body layer;

a p−

type body layer disposed above a first portion of the oxide insulation layer, the p−

type body layer including a silicon germanium (Si—

Ge) epitaxial layer, the Si—

Ge epitaxial layer including a number of recombination centers, the p−

type body layer including a number of recombination centers between the Si—

Ge epitaxial layer and the oxide insulation layer; and

an NFET device in association with the p−

type body layer.

146. The system of claim 145, wherein:

the PFET device includes a source region and a silicided lateral Schottky layer in contact with the source region and the n−

type body layer; and

the NFET device includes a source region and both a silicided lateral Schottky layer and a metal lateral Schottky layer in contact with the source region and the p−

type body layer.