Multiplier array processing system with enhanced utilization at lower precision

• US 20040015533A1
• Filed: 04/18/2003
• Published: 01/22/2004
• Est. Priority Date: 08/16/1995
• Status: Active Grant

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Massalin, Alexia, Hansen, Craig C.
• Granted Patent: US 7,509,366 B2
• Time in Patent Office: Days
• US Class Current: 708/523
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/238 Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams hybrid fiber coaxial [HFC] networks for downstream channel allocation for video distribution H04L12/2801; flow control in packet networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/23805 Controlling the feeding rate to the network, e.g. by controlling the video pump
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

Claims

1. A multiplier processing system for performing a group-multiply-and-sum instruction, said system comprising:

means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;

means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and

means for adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.

2. The multiplier processing system for performing a group-multiply-and-sum instruction according to claim 1, wherein the instruction comprises a fixed-point arithmetic operation.

3. The multiplier processing system for performing-a group-multiply-and-sum instruction according to claim 1, wherein the instruction comprises a fixed-point arithmetic operation.

4. The multiplier processing system for performing a group-multiply-and-sum instruction according to claim 1, further comprising:

means for including a third operand in the addition of said products.

5. A multiplier processing system for performing a group-multiply-sum-and-add instruction, said system comprising:

means for partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;

means for multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and

means for adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.

6. The multiplier processing system for performing a group-multiply-sum-and-add instruction according to claim 5, wherein the instruction comprises a fixed-point arithmetic operation.

7. The multiplier processing system for performing a group-multiply-sum-and-add instruction according to claim 5, wherein the instruction comprises a fixed-point arithmetic operation.

8. A method for performing a group-multiply-and-sum instruction, said method comprising the steps of:

partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;

multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and

adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.

9. The method for performing a group-multiply-and-sum instruction according to claim 8, wherein the instruction comprises a fixed-point arithmetic operation.

10. The method for performing a group-multiply-and-sum instruction according to claim 8, wherein the instruction comprises a fixed-point arithmetic operation.

11. The method for performing a group-multiply-and-sum instruction according to claim 8, further comprising:

including a third operand in the addition of said products.

12. A method for performing a group-multiply-sum-and-add instruction, said method comprising the steps of:

partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;

multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product; and

adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.

13. The method for performing a group-multiply-sum-and-add instruction according to claim 12, wherein the instruction comprises a fixed-point arithmetic operation.

14. The method for performing a group-multiply-sum-and-add instruction according to claim 12, wherein the instruction comprises a fixed-point arithmetic operation.