Heterogeneous interconnection architecture for programmable logic devices
First Claim
Patent Images
1. A programmable logic device comprising:
- a plurality of function blocks;
a first plurality of a programmable interconnect resource for programmably interconnecting at least some of said function blocks; and
a second plurality of said programmable interconnect resource for programmably interconnecting some of said function blocks, said second plurality comprising about 20% of all said programmable interconnect resource on said programmable logic device.
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Abstract
An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.
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10 Claims
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1. A programmable logic device comprising:
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a plurality of function blocks;
a first plurality of a programmable interconnect resource for programmably interconnecting at least some of said function blocks; and
a second plurality of said programmable interconnect resource for programmably interconnecting some of said function blocks, said second plurality comprising about 20% of all said programmable interconnect resource on said programmable logic device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A programmable logic device comprising:
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a plurality of function blocks; and
a first group of signal wires spaced apart from each other by a first wire-to-wire spacing and connected to at least some of said function blocks; and
a second group of signal wires spaced apart from each other by a second wire-to-wire spacing and connected to some of said function blocks, said second group of signal wires comprising about 20% of all said signal wires on said programmable logic device.
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10. A programmable logic device comprising:
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a plurality of function blocks; and
a first group of signal wires each having a first width, said first group of signal wires connected to at least some of said function blocks; and
a second of signal wires each having a second width wider than said first width, said second group of signal wires connected to some of said function blocks and comprising about 20% of all said signal wires on said programmable logic device.
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Specification