Method and apparatus for round trip delay measurement in a bi-directional, point-to-point, serial data channel

• US 20040017806A1
• Filed: 07/26/2002
• Published: 01/29/2004
• Est. Priority Date: 07/26/2002
• Status: Active Grant

• Current Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Martin, Kreg A., Yazdy, Farid A.
• Granted Patent: US 7,286,527 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 43/0864 Round trip delays
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/55 Prevention, detection or correction of errors

Abstract

The link round trip delay between two switches in a Fibre Channel network may be determined by sending a particular timing signal value from an originating switch to a responding switch. The responding switch may store the timing signal value in an “echo” register for comparison to subsequently received timing signals. The originating switch may then send the pre-selected timing signal to the responding switch while simultaneously starting a timer. When the responding switch receives the timing signal, it may compare the value of the received signal to that stored in its echo register. If the value, is the same, the responding switch may retransmit—i.e., echo—the timing signal to the originating switch. When the originating switch receives the echoed timing signal, it may stop its timer and compute the link round trip delay time. The computed link round trip delay time between the originating switch and the responding switch may be advantageously used in fabric routing algorithms.

Claims

1. A transceiver comprising:

a receiver for receiving timing signals from a remote transceiver;

a first register for storing timing signal values received from a remote transceiver;

logic circuitry for comparing data received from a remote transceiver to data stored in said first register for storing timing signals; and

,

a transmitter for transmitting a timing signal received from a remote transceiver, which timing signal is the same as the timing signal stored in said first register.

2. A transceiver as recited in claim 1 wherein the timing signal is a primitive.

7. A Fibre Channel switch as recited in claim 1 further comprising a second register for storing timing primitive signals received from a remote Fibre Channel switch which are not the same as the timing primitive signal stored in said first register.

8. A Fibre Channel switch as recited in claim 7 further comprising logic circuitry for issuing an interrupt when a timing primitive signal is stored in said second register.

3. A transceiver comprising:

a transmitter for sending a timing signal value to a remote transceiver for storage in said remote transceiver;

a register for storing the timing signal value;

a transmitter for transmitting the timing signal to said remote transceiver;

a timer which starts when said transmitter transmits the timing signal and which can be stopped;

a receiver for receiving timing signals from said remote transceiver; and

,

a comparator coupled to said receiver and said timer for stopping said timer if the received timing signal is the same as the timing signal value stored in said register.

4. A transceiver as recited in claim 3 wherein the timing signal is a primitive.

5. A transceiver as recited in claim 3 further comprising:

a receiver for receiving a timing signal value and a timing signal from a remote transceiver;

a register for storing said received timing signal value;

a transmitter for transmitting received timing signals to said remote transceiver;

a comparator coupled to said receiver and said transmitter for transmitting said timing signal if the received timing signal is the same as the received timing signal value stored in said register.

6. A Fibre Channel switch comprising:

a receiver for receiving timing primitive signals from a remote Fibre Channel switch;

a first register for storing timing primitive signal values received from a remote Fibre Channel switch;

logic circuitry for comparing data received from a remote Fibre Channel switch to data stored in said first register for storing timing primitive signals; and

,

a transmitter for transmitting a timing primitive signal received from a remote Fibre Channel switch, which timing primitive signal is the same as the timing primitive signal stored in said first register.

9. A Fibre Channel switch comprising:

a transmitter for sending a timing primitive signal value to a remote Fibre Channel switch for storage in said remote Fibre Channel switch;

a register for storing the timing primitive signal value;

a transmitter for transmitting the timing primitive signal to said remote Fibre Channel switch;

a timer which starts when said transmitter transmits the timing primitive signal and which can be stopped;

a receiver for receiving timing primitive signals from said remote Fibre Channel switch; and

,

a comparator coupled to said receiver and said timer for stopping said timer if the received timing primitive signal is the same as the timing primitive signal value stored in said register.

10. A Fibre Channel switch as recited in claim 9 further comprising:

a receiver for receiving a timing primitive signal value and a timing primitive signal from a remote Fibre Channel switch;

a register for storing said received timing primitive signal value;

a transmitter for transmitting received timing primitive signals to said remote Fibre Channel switch;

a comparator coupled to said receiver and said transmitter for transmitting said timing primitive signal if the received timing primitive signal is the same as the received timing primitive signal value stored in said register.

11. A method for measuring the link round trip delay between two Fibre Channel switches comprising:

selecting a timing primitive signal;

storing the selected timing primitive signal in a first register in a first switch;

sending the selected timing primitive signal to a second switch;

storing the selected timing primitive signal in a second register in said second switch;

transmitting the selected timing primitive signal from said first switch to said second switch;

starting a timer when the selected timing primitive signal is transmitted by said first switch;

receiving a primitive signal in said second switch;

comparing the received primitive signal to the selected timing primitive signal stored in said second register;

transmitting the received primitive signal from said second switch to said first switch if said received primitive signal is the same as the timing primitive signal stored in said second register;

receiving said primitive signal transmitted by said second switch in said first switch;

comparing said received primitive signal transmitted by said second switch to the selected timing primitive signal in said first register; and

,

stopping the timer if said received primitive signal transmitted by said second switch is the same as the timing primitive signal stored in said first register.

12. A method as recited in claim 11 further comprising storing timer counts in a third register in said first switch in response to a cyclic clock signal and computing the link round trip delay time from the clock cycle rate and the number of timer counts in said third register.

13. A method as recited in claim 12 further comprising using said computed link round trip delay time in a routing algorithm for a Fibre Channel fabric.

14. A method as recited in claim 11 further comprising stopping the timer and generating a interrupt signal if the timer count exceeds a selected value.

15. A method as recited in claim 11 further comprising storing clock counts in a register which rolls over when its maximum value is exceeded and incrementing a counter each time said rollover occurs.

16. A method as recited in claim 11 further comprising enabling retransmission of selected timing primitive signals in said second switch prior to transmitting said timing primitive signal from said first switch.

17. A method as recited in claim 16 further comprising disabling retransmission of selected timing primitive signals in said second switch subsequent to receiving said timing primitive signal by said first switch.

18. A method as recited in claim 11 further comprising storing a received timing primitive signal in a third register in said second switch if said received timing primitive signal does not match said selected timing primitive signal stored in said second register.

19. A method as recited in claim 18 further comprising generating an interrupt signal in response to storing said received timing primitive signal is said third register.

20. A method as recited in claim 19 further comprising initiating an error detection process in response to said interrupt signal.

21. A method as recited in claim 19 further comprising restarting said link round trip delay measurement in response to said interrupt signal.

22. An article comprising a medium storing instructions that enable a first processor-based system to:

select a timing primitive signal;

store the selected timing primitive signal in a first register;

send the selected timing primitive signal value to a second processor-based system;

transmit the selected timing primitive signal from said first processor-based system to said second processor-based system;

start a timer when the selected timing primitive signal is transmitted by said first processor-based system; and

,

compute the time elapsed from transmitting the selected timing primitive signal to receiving the selected timing primitive signal from said second processor-based system.

23. An article as recited in claim 22 further comprising stored instructions that enable a first processor-based system to:

receive a timing signal primitive value from said second processor-based system;

store said timing primitive signal value in a second register; and

,

enable, in response to a command received from said second processor-based system, the retransmission of said received timing primitive signal if said received timing primitive signal has the same value as that stored in said second register.

24. An article as recited in claim 23 further comprising stored instructions that enable a first processor-based system to read a received primitive signal stored in a third register if the value of the received primitive signal differs from that in said first register and said second register.

25. An article comprising a medium storing instructions that enable a first processor-based system to:

store a timing primitive signal value received from a second processor-based system in a register; and

,

enable, in response to a command from a second processor-based system, the transmission of a received timing primitive signal to said second processor-based system if said received timing primitive signal has the same value as that stored in said register.

26. A processor-based system comprising:

a processor; and

,

a data storage medium coupled to said processor and storing instructions enabling said processor to;

select a timing primitive signal;

store the selected timing primitive signal in a first register;

send the selected timing primitive signal value to a second processor-based system;

transmit the selected timing primitive signal from said first processor-based system to said second processor-based system;

start a timer when the selected timing primitive signal is transmitted by said first processor-based system; and

,

compute the time elapsed from transmitting the selected timing primitive signal to receiving the selected timing primitive signal from said second processor-based system.

27. A processor-based system as recited in claim 26 further comprising stored instructions enabling the processor to:

receive a timing signal primitive value from said second processor-based system;

store said timing primitive signal value in a second register; and

,

enable, in response to a command received from said second processor-based system, the retransmission of said received timing primitive signal if said received timing primitive signal has the same value as that stored in said second register.

28. A processor-based system as recited in claim 27 further comprising stored instructions that enable said first processor-based system to:

read a received primitive signal stored in a third register if the value of the received primitive signal differs from that in said first register and said second register

29. A processor-based system comprising:

a processor; and

,

a data storage medium coupled to said processor and storing instructions enabling said processor to;

store a timing primitive signal value received from a second processor-based system in a register; and

,

enable, in response to a command from a second processor-based system, the transmission of a received timing primitive signal to said second processor-based system if said received timing primitive signal has the same value as that stored in said register.

30. A Fibre Channel fabric comprising:

a first Fibre Channel switch;

a second Fibre Channel switch;

a link connecting said first and second switches;

a receiver in said first Fibre Channel switch for receiving timing primitive signals from said second Fibre Channel switch;

a first register in said first Fibre Channel switch for storing timing primitive signal values received from said second Fibre Channel switch; and

, logic circuitry in said first Fibre Channel switch for comparing the value of a timing primitive signal received from said second Fibre Channel switch to the timing primitive signal value stored in said first register for storing timing primitive signals.

31. A Fibre Channel fabric as recited in claim 30 further comprising a transmitter in said first Fibre Channel switch for transmitting a timing primitive signal received from said second Fibre Channel switch, which timing primitive signal is the same as the timing primitive signal stored in said first register.

32. A Fibre Channel fabric comprising:

a first Fibre Channel switch;

a second Fibre Channel switch;

a link connecting said first and second Fibre Channel switches,

wherein said first Fibre Channel switch includes;

a receiver for receiving timing primitive signals from said second Fibre Channel switch;

a first register for storing timing primitive signal values received from said second Fibre Channel switch;

logic circuitry for comparing data received from said second Fibre Channel switch to data stored in said first register for storing timing primitive signals; and

,

a transmitter for transmitting a timing primitive signal received from said second Fibre Channel switch, which timing primitive signal is the same as the timing primitive signal stored in said first register, and

wherein said second Fibre Channel switch includes;

a transmitter for sending a timing primitive signal value to said first Fibre Channel switch for storage in said first register;

a second register for storing the timing primitive signal value;

a transmitter for transmitting the timing primitive signal to said first Fibre Channel switch;

a timer which starts when said transmitter transmits the timing primitive signal and which can be stopped;

a receiver for receiving timing primitive signals from said first Fibre Channel switch; and

,

a comparator coupled to said receiver and said timer for stopping said timer if the received timing primitive signal is the same as the timing primitive signal stored in said second register.

33. A network comprising:

a first end node coupled to a first Fibre Channel switch;

a second end node coupled to a second Fibre Channel switch;

a link connecting said first and second Fibre Channel switches;

a receiver in said first Fibre Channel switch for receiving timing primitive signal values from said second Fibre Channel switch;

a first register in said first Fibre Channel switch for storing timing primitive signal values received from said second Fibre Channel switch; and

,

logic circuitry in said first Fibre Channel switch for comparing the value of a timing primitive signal received from said second Fibre Channel switch to the timing primitive signal value stored in said first register for storing timing primitive signal values.

34. A network as recited in claim 33 further comprising a transmitter in said first Fibre Channel switch for transmitting a timing primitive signal received from said second Fibre Channel switch, which timing primitive signal is the same as the timing primitive signal value stored in said first register.

35. A network as recited in claim 33 further comprising a transmitter in said second Fibre Channel switch for sending a timing primitive signal value to said first Fibre Channel switch.

36. A network comprising:

a first end node;

a first Fibre Channel switch coupled to said first end node;

a second end node;

a second Fibre Channel switch coupled to said second end node; and

,

a link connecting said first and second Fibre Channel switches;

wherein said first Fibre Channel switch includes;

a receiver for receiving timing primitive signals from said second Fibre Channel switch;

a first register for storing timing primitive signal values received from said second Fibre Channel switch;

logic circuitry for comparing data received from said second Fibre Channel switch to data stored in said first register for storing timing primitive signals; and

,

a transmitter for transmitting a timing primitive signal received from said second Fibre Channel switch, which timing primitive signal is the same as the timing primitive signal stored in said first register, and

wherein said second Fibre Channel switch includes;

a transmitter for sending a timing primitive signal value to said first Fibre Channel switch for storage in said first register;

a second register for storing the timing primitive signal value;

a transmitter for transmitting the timing primitive signal to said first Fibre Channel switch;

a timer which starts when said transmitter transmits the timing primitive signal and which can be stopped;

a receiver for receiving timing primitive signals from said first Fibre Channel switch; and

,

a comparator coupled to said receiver and said timer for stopping said timer if the received timing primitive signal is the same as the timing primitive signal stored in said second register.

37. A network as recited in claim 36 wherein said first Fibre Channel switch further includes a third register for storing a received timing primitive signal which is not the same as the timing primitive signal is said first register.