Method and apparatus for producing a silicon wafer chip package

• US 20040018667A1
• Filed: 07/26/2002
• Published: 01/29/2004
• Est. Priority Date: 07/26/2002
• Status: Abandoned Application

• Current Assignee: Haren Joshi, Ralph Alan Griffin
• Original Assignee: Haren Joshi, Ralph Alan Griffin
• Inventors: Joshi, Haren, Griffin, Ralph Alan
• Application Number:
  US10/206,281
• Publication Number:
  US 20040018667A1
• Time in Patent Office: Days
• US Class Current: 438/126
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method for packaging discrete and integrated circuit (IC) die each having a pattern of input/output (I/O) pads has steps of (a) forming a first pattern of openings through a thickness of a silicon substrate wafer in a plurality of die attach positions, and metallizing through the openings; (b) attaching the IC die to a first surface of the wafer in individual ones of the plurality of positions; (c) electrically connecting individual ICs from the I/O pads to the metallized vias; (d) covering the attached and I/O-connected ICs on the first surface with an encapsulation material, forming a laminate encapsulating the ICs on the wafer; and (e) singulating the laminate into individual packages comprising at least one encapsulated IC on a silicon substrate having a pattern of electrical contacts on an outside surface of the substrate communicating electrically with I/O pads on the encapsulated IC. The substrate wafer can be a reclaimed wafer.

Claims

1. A method for packaging integrated circuit (IC) die each having a pattern of input/output (I/O) pads, comprising the steps of:

(a) forming a first pattern of openings through a thickness of a silicon substrate wafer in a plurality of die attach positions, and metallizing through the openings;

(b) attaching the IC die to a first surface of the wafer in individual ones of the plurality of positions;

(c) electrically connecting individual ICs from the I/O pads to the metallized vias;

(d) covering the attached and I/O-connected ICs on the first surface with an encapsulation material, forming a laminate encapsulating the ICs on the wafer; and

(e) singulating the laminate into individual packages comprising at least one encapsulated IC on a silicon substrate having a pattern of electrical contacts on an outside surface of the substrate communicating electrically with I/O pads on the encapsulated IC.

2. The method of claim 1 wherein the wafer is a reclaimed wafer having circuitry on an active surface, and further comprising a step for removing the circuitry and thinning the wafer.

3. The method of claim 1 wherein in step (d) the encapsulation material is a polymer material.

4. The method of claim 3 wherein the polymer material is applied by one of spinning or molding.

5. The method of claim 1 further comprising a step or steps for forming electrical bonding pads or conductive traces on one or both sides of the substrate wafer.

6. The method of claim 1 further comprising steps for applying dielectric material at individual ones of the die attach positions, forming die attach pads for mounting individual ones of the IC die.

7. The method of claim 1 wherein electrical connection is made by one of wire bonding or flip-chip techniques.

8. The method of claim 1 further comprising a step before singulation for electrically testing individual ones of the encapsulated die.

9. The method of claim 1 further comprising a step for forming solder bumps electrically connected to the metallized vias on the side of the wafer opposite the encapsulated IC die, to facilitate subsequent mounting of singulated packages to printed circuit boards or other circuitry.

10. The method of claim 1 wherein in step (d) the encapsulation material is a second silicon wafer having cavities in one surface in the pattern of the plurality of die attach positions, and further comprising a step for joining the two wafers surface to surface such that individual ones of the attached die are enclosed in individual ones of the cavities.

11. The method of claim 10 wherein the two wafers are joined by a glass fritseal.

12. The method of claim 1 wherein the encapsulation material is formed from a spacer wafer having through-openings of a size to enclose individual die attached to positions on the substrate wafer, and a cap wafer, wherein the spacer wafer is joined to the substrate wafer surrounding individual ones of the attached die, and the cap wafer is joined to the spacer wafer as a lid, completing enclosure of the individual die.

13. The method of claim 12 wherein the joining of wafer to wafer is by a glass fritseal.

14. An integrated circuit (IC) package, comprising:

(a) a silicon substrate having a pattern of metal-filled through-openings between a first and a second side;

(b) an IC die attached to the silicon substrate on a first side;

(c) electrical connections from input-output (I/O) pads on the die to the metal-filled through openings; and

(d) an encapsulation structure encapsulating the die and electrical connections on the first side of the substrate.

15. The package of claim 14 wherein the substrate is from a reclaimed wafer having circuitry on an active surface, and the circuitry is removed, thinning the wafer, before the die is mounted.

16. The package of claim 14 wherein encapsulation structure is a polymer material completely covering the die and the connections.

17. The package of claim 16 wherein the polymer material is applied by one of spinning or molding.

18. The package of claim 14 further comprising electrical bonding pads or conductive traces on one or both sides of the substrate.

19. The package of claim 14 further comprising a dielectric die attach pad upon which the die is mounted.

20. The package of claim 14 wherein the electrical connections are wires from the die I/O pads to the metal-filled through openings.

21. The package of claim 14 further comprising solder bumps electrically connected to the metal-filled through-openings on a second side of the substrate.

22. The package of claim 14 wherein the encapsulation structure comprises a silicon enclosure element having a cavity in one surface of an extent and volume to enclose the mounted die and connections, wherein the silicon substrate and the enclosure element are joined to completely encapsulate the die and connections.

23. The package of claim 22 wherein the silicon substrate and the silicon enclosure element are joined by a glass fritseal.

24. The package of claim 14 wherein the encapsulation structure comprises a spacer wafer having a through-opening of a size to enclose the die and connections, and a cap wafer, the spacer wafer joined to the substrate wafer and the cap wafer joined to the spacer wafer as a lid, completing enclosure of the die.

25. The package of claim 24 wherein the joining of silicon to silicon is by a glass fritseal.