SEMICONDUCTOR DICE HAVING BACKSIDE REDISTRIBUTION LAYER ACCESSED USING THROUGH-SILICON VIAS, METHODS OF FABRICATION AND ASSEMBLIES

• US 20040021139A1
• Filed: 07/31/2002
• Published: 02/05/2004
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Murphy, Tim E., Jackson, Timothy L.
• Granted Patent: US 6,800,930 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

Claims

1. A semiconductor substrate comprising:

at least one semiconductor die having an active surface and a back surface, the at least one semiconductor die defining at least one via therethrough extending from the active surface to the back surface thereof;

an electrically conductive material disposed in the at least one via and substantially extending a length thereof from the active surface to the back surface; and

at least one electrically conductive redistribution line on the back surface in electrical communication with the electrically conductive material in the at least one via and extending to a predetermined location on the back surface and remote from the at least one via.

2. The substrate of claim 1, wherein the at least one semiconductor die comprises a wafer.

3. The substrate of claim 1, wherein the at least one semiconductor die comprises multiple, unsingulated semiconductor dice.

4. The substrate of claim 1, further comprising at least one trace disposed on the active surface of the at least one semiconductor die and electrically connected to the electrically conductive material in the at least one via.

5. The substrate of claim 4, wherein the at least one trace electrically connects active circuitry on the active surface to the electrically conductive material in the at least one via.

6. The substrate of claim 1, wherein the at least one semiconductor die includes at least one inner sidewall having a dielectric layer thereover, the electrically conductive material residing within the dielectric layer.

14. The substrate of claim 1, wherein the at least one via comprises a plurality of vias, the at least one redistribution line comprises a plurality of redistribution lines, each in electrical communication with the electrically conductive material of a via of the plurality, and wherein the predetermined locations of the redistribution lines form, in combination, a pattern corresponding to a pattern of interconnects of another substrate to be superimposed with the substrate.

15. The substrate of claim 14, further including electrically conductive bumps disposed over the predetermined locations of the redistribution lines of the plurality and projecting transversely from the back surface.

16. The substrate of claim 15, wherein the electrically conductive bumps include at least one of a metal, an alloy, a conductive polymer and a conductor-filled polymer.

17. The substrate of claim 16, wherein the electrically conductive bumps comprise solder.

18. The substrate of claim 1, wherein the electrically conductive material of the at least one via is in direct electrical connection with integrated circuitry formed on the active surface.

19. The substrate of claim 18, wherein the at least one via includes a bond pad formed thereover on the active surface.

20. The substrate of claim 18, further including at least one electrically conductive redistribution line formed over the active surface, electrically connected to the electrically conductive material of the at least one via proximate the active surface and extending to a predetermined location remote therefrom on the active surface.

21. The substrate of claim 20, wherein the predetermined location comprises a location of an interconnect of another substrate to be superimposed on the active surface.

22. A semiconductor device assembly comprising:

at least one semiconductor die having an active surface and a back surface, the at least one semiconductor die defining at least one via therethrough extending from the active surface to the back surface thereof;

an electrically conductive material disposed in the at least one via and substantially extending a length thereof from the active surface to the back surface;

at least one electrically conductive redistribution line in electrical communication with the electrically conductive material in the at least one via to a predetermined location on the back surface; and

a substrate having a first surface and a second surface and at least one electrical interconnect on the first surface, the substrate being superimposed over the at least one semiconductor die with the at least one electrical interconnect on the first surface electrically connected to the at least one redistribution line at the predetermined location on the back surface of the at least one semiconductor die.

23. The assembly of claim 22, wherein the at least one via comprises a plurality of vias, at least some of the vias having electrically conductive redistribution lines extending therefrom to respective predetermined locations on the back surface of the at least one semiconductor die and wherein the at least one electrical interconnect comprises a plurality of electrical interconnects and at least some of the redistribution lines are electrically connected to at least some of the electrical interconnects by conductive bumps extending transversely between the at least one semiconductor die and the substrate.

24. The assembly of claim 23, further including a dielectric filler material disposed between the back surface of the at least one semiconductor die and the first surface of the substrate.

25. The assembly of claim 22, wherein the substrate comprises a carrier substrate.

26. The assembly of claim 25, wherein the carrier substrate is an interposer, a printed circuit board or a semiconductor substrate.

27. The assembly of claim 25, wherein the substrate comprises at least one of a BT resin, a ceramic, an FR-4 laminate, an FR-5 laminate, and a semiconductor material.

28. The assembly of claim 22, wherein the back surface of the at least one semiconductor die comprises at least one electrical component formed thereon.

29. The assembly of claim 28, wherein the at least one electrical component comprises at least one of a capacitor, an inductor, a resistor, a fuse and a controller.

30. The assembly of claim 28, wherein the at least one electrical component is electrically connected to the at least one redistribution line.

31. The assembly of claim 30, wherein the at least one electrical component is formed as part of the at least one redistribution line.

32. The assembly of claim 22, wherein the at least one semiconductor die comprises a wafer.

33. The assembly of claim 22, wherein the at least one semiconductor die comprises multiple, unsingulated semiconductor dice.

34. The assembly of claim 22, further comprising at least one trace disposed on the active surface of the at least one semiconductor die and electrically connected to the electrically conductive material in the at least one via.

35. The assembly of claim 34, wherein the at least one trace electrically connects active circuitry on the active surface to the electrically conductive material in the at least one via.

36. The assembly of claim 22, wherein the at least one semiconductor die includes at least one inner side wall having a dielectric layer thereover, the electrically conductive material residing within the dielectric layer.

37. The assembly of claim 22, wherein the electrically conductive material within the at least one via includes at least one of a metal, an alloy, a conductive polymer, a conductor-filled polymer and a conductively-doped portion of a semiconductor material matrix of the semiconductor die.

38. The assembly of claim 22, wherein electrically conductive material of the at least one redistribution line includes at least one of a metal, an alloy, a conductive polymer and a conductor-filled polymer.

39. The assembly of claim 22, wherein the at least one via comprises a plurality of vias, the at least one redistribution line comprises a plurality of redistribution lines, each in electrical communication with the electrically conductive material of a via of the plurality, the at least one electrical interconnect comprises a plurality of electrical interconnects and wherein the predetermined locations of the redistribution lines form, in combination, a pattern corresponding to a pattern of the plurality of electrical interconnects of the substrate.

40. The assembly of claim 39, further including electrically conductive bumps disposed over the predetermined locations of the redistribution lines of the plurality and projecting transversely from the back surface in contact with the electrical interconnects of the plurality.

41. The assembly of claim 40, wherein the electrically conductive bumps include at least one of a metal, an alloy, a conductive polymer and a conductor-filled polymer.

42. The assembly of claim 41, wherein the electrically conductive bumps comprise solder.

43. The assembly of claim 22, wherein the electrically conductive material of the at least one via is in direct electrical connection with integrated circuitry formed on the active surface.

44. The assembly of claim 43, wherein the at least one via includes a bond pad formed thereover on the active surface.

45. The assembly of claim 43, further including at least one electrically conductive redistribution line formed over the active surface, electrically connected to the electrically conductive material of the at least one via proximate the active surface and extending to a predetermined location remote therefrom on the active surface.

46. The assembly of claim 45, wherein the predetermined location comprises a location of an interconnect of another substrate to be superimposed on the active surface.

53. The stacked assembly of claim 28, further comprising a third semiconductor die having an active surface and a back surface, the third semiconductor die electrically connected to the second semiconductor die.

54. The stacked assembly of claim 53, wherein the third semiconductor die comprises:

at least one via extending from the active surface to the back surface thereof;

a conductive material disposed in the at least one via of the third semiconductor die and substantially extending a length thereof from the active surface to the back surface thereof; and

at least one redistribution line in electrical communication with the conductive material in the at least one via of the third semiconductor die and extending to a predetermined location on the back surface thereof.

55. The stacked assembly of claim 54, wherein the at least one redistribution line on the back surface of the third semiconductor die is electrically connected to the active surface of the second semiconductor die at the predetermined location of the at least one redistribution line of the third semiconductor die with an electrically conductive bump extending transversely therebetween.

56. The stacked assembly of claim 55, wherein the active surface of the third semiconductor die includes at least one wire bond extending therefrom to the first surface of the substrate.

57. The stacked assembly of claim 56, further comprising an encapsulation material formed at least over the at least one wire bond.

58. The stacked assembly of claim 53, wherein the active surface of the third semiconductor die is electrically connected to the active surface of the second semiconductor die with electrically conductive bumps extending transversely therebetween.

47. A stacked semiconductor device assembly comprising:

a first semiconductor die having an active surface and a back surface, the first semiconductor die defining at least one via therethrough extending from the active surface to the back surface thereof;

a conductive material disposed in the at least one via and substantially extending a length thereof from the active surface to the back surface;

at least one electrically conductive redistribution line in electrical communication with the conductive material in the at least one via and extending to a predetermined location on the back surface;

a substrate having a first surface and a second surface and at least one electrical interconnect on the first surface, the at least one electrical interconnect on the first surface electrically connected to the at least one redistribution line at the predetermined location on the back surface; and

a second semiconductor die having an active surface and a back surface, the second semiconductor die electrically connected to the active surface of the first semiconductor die.

48. The stacked assembly of claim 47, wherein the second semiconductor die comprises:

at least one via extending from the active surface to the back surface of the second semiconductor die;

a conductive material disposed in the at least one via of the second semiconductor die and substantially extending a length thereof from the active surface to the back surface thereof; and

at least one electrically conductive redistribution line in electrical communication with the conductive material in the at least one via of the second semiconductor die and extending to a predetermined location on the back surface of the second semiconductor die.

49. The stacked assembly of claim 48, wherein the at least one redistribution line on the back surface of the second semiconductor die is electrically connected to the active surface of the first semiconductor die with an electrically conductive bump extending transversely therebetween.

50. The stacked assembly of claim 49, wherein the active surface of the second semiconductor die includes at least one wire bond extending therefrom to the first surface of the substrate.

51. The stacked assembly of claim 50, further comprising an encapsulation material formed at least over the at least one wire bond.

52. The stacked assembly of claim 47, wherein the active surface of the second semiconductor die is electrically connected to the active surface of the first semiconductor die with electrically conductive bumps extending transversely therebetween.

59. The stacked assembly of claim 47, wherein the back surface of the first semiconductor die comprises at least one electrical component formed thereon.

60. The stacked assembly of claim 59, wherein the at least one electrical component comprises at least one of a capacitor, an inductor, a resistor, a fuse and a controller.

61. The stacked assembly of claim 59, wherein the at least one electrical component is electrically connected to the at least one redistribution line.

62. The stacked assembly of claim 61, wherein the at least one electrical component is formed as part of the at least one redistribution line.

63. A method of making a semiconductor substrate, the method comprising:

providing at least one semiconductor die having an active surface and a back surface, the at least one semiconductor die defining at least one via therethrough extending from the active surface to the back surface thereof;

disposing conductive material in the at least one via to substantially extend therethrough from the active surface to the back surface of the at least one semiconductor die; and

forming at least one electrically conductive redistribution line on the back surface of the at least one semiconductor die in electrical communication with the conductive material in the at least one via and extending to a predetermined location on the back surface of the at least one semiconductor die.

64. The method of claim 63, wherein providing comprises:

forming the at least one via in the active surface of the at least one semiconductor die to extend partially through the at least one semiconductor die;

filling the at least one via with the conductive material; and

removing material from the back surface of the at least one semiconductor die to expose the conductive material in the at least one via.

65. The method of claim 64, wherein forming the at least one via comprises at least one of drilling and laser ablation.

66. The method of claim 64, wherein filling comprises depositing conductive material over the active surface to fill the at least one via.

67. The method of claim 64, wherein removing comprises:

grinding material from the back surface of the at least one semiconductor die; and

applying at least one of a wet etch and a dry etch on the back surface to expose the conductive material on the back surface.

68. The method of claim 64, wherein removing comprises abrasively removing.

69. The method of claim 64, wherein removing comprises:

grinding the material from the back surface of the at least one semiconductor die; and

abrasively polishing the back surface to expose the conductive material on the back surface and to planarize the back surface.

70. The method of claim 63, wherein disposing the conductive material comprises doping a matrix material of the at least one semiconductor die to simultaneously define the at least one via and render it conductive.

71. The method of claim 63, wherein forming comprises:

depositing a redistribution layer precursor on the back surface of the at least one semiconductor die; and

patterning the redistribution layer to define the at least one redistribution line on the back surface.

72. The method of claim 71, wherein patterning comprises selectively masking and etching the redistribution layer precursor to remove excess material of the redistribution layer precursor to form the at least one redistribution line on the back surface.

73. The method of claim 63, wherein forming comprises printing the at least one redistribution line on the back surface.

74. The method of claim 63, wherein forming comprises applying the at least one redistribution line as a preform to the back surface.

75. The method of claim 63, wherein forming comprises positioning a conductive bump on a portion of the at least one redistribution line proximate the predetermined location.

76. A method of assembling a semiconductor assembly comprising:

providing a substrate having a first surface and a second surface and at least one electrical interconnect on the first surface;

providing a first semiconductor die having an active surface bearing integrated circuitry and a back surface, the first semiconductor die defining at least one via extending from the active surface to the back surface with conductive material formed therein, the back surface having at least one redistribution line thereon extending from the conductive material in the at least one via to a predetermined location on the back surface; and

attaching the back surface of the first semiconductor die to the first surface of the substrate so that the at least one electrical interconnect on the first surface is electrically connected to the at least one redistribution line at the predetermined location on the back surface of the first semiconductor die.

77. The method of claim 76, wherein the electrically connecting comprises connecting the at least one redistribution line on the back surface of the first semiconductor die to the at least one electrical interconnect with a conductive bump extending transversely therebetween.

78. The method of claim 77, further comprising applying a dielectric filler material between the back surface of the first semiconductor die and the first surface of the substrate to fill a gap therebetween.

79. The method of claim 76, wherein the at least one redistribution line comprises a plurality of redistribution lines and the at least one electrical interconnect comprises a plurality of electrical interconnects, wherein the predetermined locations of the redistribution lines of the plurality are located to correspond to a pattern of the plurality of electrical interconnects.

80. The method of claim 76, further comprising providing a second semiconductor die having an active surface bearing integrated circuitry and a back surface and electrically connecting the second semiconductor die to the active surface of the first semiconductor die.

81. The method of claim 80, wherein providing the second semiconductor die comprises providing the second semiconductor die to define at least one via extending from the active surface to the back surface thereof with conductive material formed therein, the back surface of the second semiconductor die having at least one redistribution line thereon in electrical communication with the conductive material in the at least one via thereof and extending to a predetermined location on the back surface of the second semiconductor die.

82. The method of claim 81, further comprising electrically connecting the back surface of the second semiconductor die to the active surface of the first semiconductor die so that at least one conductive element on the active surface of the first semiconductor die is electrically connected to the at least one redistribution line at the predetermined location on the back surface of the second semiconductor die.

83. The method of claim 82, further comprising forming wire bonds from the active surface of the second semiconductor die to the first surface of the substrate.

84. The method of claim 83, further comprising encapsulating at least the wire bonds with encapsulation material.

85. The method of claim 82, wherein electrically connecting the back surface of the second semiconductor die to the active surface of the first semiconductor die comprises connecting the at least one redistribution line on the back surface of the second semiconductor die to the at least one conductive element with a conductive bump.

86. The method of claim 85, further comprising applying a dielectric filler material between the back surface of the second semiconductor die and the active surface of the first semiconductor die to fill a gap therebetween.

87. The method of claim 80, further comprising electrically connecting the active surface of the second semiconductor die to the active surface of the first semiconductor die with conductive bumps therebetween.

89. The method of claim 80, further comprising providing a third semiconductor die having an active surface bearing integrated circuitry and a back surface.

90. The method of claim 89, further comprising electrically connecting the active surface of the second semiconductor die to the active surface of the first semiconductor die with conductive bumps therebetween.

88. The method of claim 88, further comprising applying a dielectric filler material between the active surface of the second semiconductor die and the active surface of the first semiconductor die to fill a gap therebetween.

91. An electronic system comprising:

a processor device coupled to an input device and an output device; and

a semiconductor device assembly coupled to at least one of the processor device, the input device and the output device, the semiconductor device assembly comprising;

at least one semiconductor die having an active surface and a back surface, the at least one semiconductor die defining at least one via therethrough extending from the active surface to the back surface thereof;

a conductive material disposed in the at least one via and substantially extending a length thereof from the active surface to the back surface of the at least one semiconductor die;

at least one electrically conductive redistribution line in electrical communication with the conductive material in the at least one via and extending to a predetermined location on the back surface of the at least one semiconductor die; and

a substrate having a first surface and a second surface and at least one electrical interconnect on the first surface, the at least one electrical interconnect on the first surface electrically connected to the at least one redistribution line at the predetermined location on the back surface of the at least one semiconductor die.

92. The system of claim 91, wherein the at least one via comprises a plurality of vias, at least some of the vias having electrically conductive redistribution lines extending therefrom to respective predetermined locations on the back surface of the at least one semiconductor die and wherein the at least one electrical interconnect comprises a plurality of electrical interconnects and at least some of the redistribution lines are electrically connected to at least some of the electrical interconnects by conductive bumps extending transversely between the at least one semiconductor die and the substrate.

93. The system of claim 92, further including a dielectric filler material disposed between the back surface of the at least one semiconductor die and the first surface of the substrate.

94. The system of claim 91, wherein the back surface of the at least one semiconductor die comprises at least one electrical component formed therein.

95. The system of claim 94, wherein the at least one electrical component comprises at least one of a capacitor, an inductor, a resistor, a fuse and a controller.