Overvoltage protection device using pin diodes

• US 20040021178A1
• Filed: 07/30/2002
• Published: 02/05/2004
• Est. Priority Date: 07/30/2002
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Larson, William
• Granted Patent: US 6,822,295 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device and method of manufacture for a low capacitance overvoltage protection device. This is accomplished through the use of PiN diodes to shunt overvoltage away from internal circuit elements. PiN diodes are useful because they exhibit a low capacitance in reverse bias mode. Radio frequency integrated circuits and other integrated circuits operated at high frequency are sensitive to capacitance. This invention protects against circuit damage due to overvoltage events while keeping capacitance low through the use of PiN diodes.

Claims

1. An overvoltage protection device comprising:

a signal node for receiving and conveying a signal voltage;

an internal circuitry node electrically interconnected to said signal node;

a positive voltage PiN diode electrically connected to said signal node and to a positive voltage source whereby said positive voltage PiN diode has its forward direction from said signal node to said positive voltage source wherein said positive voltage PiN diode is in a reverse bias mode when a voltage at said signal node is within a predetermined voltage range, and wherein said positive voltage PiN diode is in a forward bias mode when a voltage present at said signal node is above said predetermined voltage range, and wherein said positive voltage PiN diode, while in said reverse bias mode, exhibits a capacitance in the range of 10 to 20 fF, and

a negative voltage PiN diode electrically connected to said signal node and to a negative voltage source whereby said negative voltage PiN diode has its forward direction from said negative voltage source to said signal node wherein said negative voltage PiN diode is in a reverse bias mode when a voltage at said signal is within a predetermined voltage range, and wherein said negative voltage PiN diode is in a forward bias mode when a voltage present at said signal node is below said predetermined voltage range, and wherein said positive voltage PiN diode, while in said reverse bias mode, exhibits a capacitance in the range of 10 to 20 fF.

2. The overvoltage protection device of claim 1 wherein said overvoltage protection device is incorporated into an integrated circuit.

3. The overvoltage protection device of claim 2 wherein the integrated circuit is fabricated on a high-resistivity silicon on insulator (SOI) wafer.

4. The overvoltage protection device of claim 1 further comprising:

a breakdown device electrically connected between the positive supply voltage and the negative supply voltage wherein the breakdown device provides an additional shunt current path.

5. The overvoltage protection device of claim 1 wherein the breakdown device comprises an element selected from the group consisting of Zener diode, Zener diode in series with PN junction diode, Zener diode in series with PiN diode, and TVS diode.

6. The overvoltage protection device of claim 5 further comprising a limiting circuit element electrically connected between the signal node and the internal circuitry node whereby said additional limiting circuit element is selected from the group consisting of capacitor, resistor, capacitor in series with resistor, capacitor in parallel with resistor.

7. The overvoltage protection device of claim 1 further comprising a limiting circuit element electrically connected between the signal node and the internal circuitry node whereby said additional limiting circuit element is selected from the group consisting of capacitor, resistor, capacitor in series with resistor, capacitor in parallel with resistor.

8. An electrostatic discharge (ESD) protection circuit fabricated as part of a SOI integrated circuit comprising:

a signal node for receiving and conveying a signal voltage;

a sink node;

at least one PiN diode for shunting voltage events away from the signal node to the sink node whereby said at least one PiN diode is in a reverse bias mode when a voltage at said signal node is within a predetermined range, and wherein said at least one PiN diode is in a forward bias mode when a voltage at said signal node is outside said predetermined range, and wherein a capacitance of said at least one PiN diode while in said reverse bias mode is less than 20 fF per PiN device.

9. The ESD protection circuit fabricated as part of a SOI integrated circuit of claim 8 further comprising a breakdown device electrically connected between said at least one PiN diode and said sink node wherein said breakdown device provides an additional shunt current path for an ESD event.

10. The ESD protection circuit fabricated as part of a SOI integrated circuit of claim 9 wherein the breakdown device comprises an element selected from the group consisting of Zener diode, Zener diode in series with PN junction diode, Zener diode in series with PiN diode, and TVS diode.

11. An overvoltage protection device comprising:

a signal node for receiving and conveying a signal voltage;

an internal circuitry node electrically interconnected to said signal node;

a positive voltage source;

a negative voltage source;

a first PiN diode electrically connected to said signal node and to said positive voltage source whereby said first PiN diode has its forward direction from said signal node to said positive voltage source;

a second PiN diode electrically connected to said signal node and to said negative voltage source whereby said second PiN diode has its forward direction from said negative voltage source to said signal node;

a third PiN diode electrically connected to said internal circuitry node and to said positive voltage source whereby said third PiN diode has its forward direction from said internal circuitry node to said positive voltage source;

a fourth PiN diode electrically connected to said internal circuitry node and said negative voltage source whereby said fourth PiN diode has its forward direction from said negative voltage source to said signal node; and

a capacitor electrically connected to said signal node and to said circuit element

whereby an electric surge at the signal node is substantially shunted away from the internal circuitry node.

12. The overvoltage protection device of claim 11 further comprising a breakdown device electrically connected between the positive voltage source and the negative voltage source.

13. The overvoltage protection device of claim 12 wherein the breakdown device comprises an element selected from the group consisting of Zener diode, Zener diode in series with PN diode, Zener diode in series with PiN diode, and TVS diode.

14. The overvoltage protection device of claim 11 wherein each PiN diode has a PiN diode periphery of approximately 50 μ

m.

15. The overvoltage protection device of claim 11 wherein each PiN diode has a capicatance of approximately 0.2 fF per micron of diode periphery.

16. The overvoltage protection device of claim 11 wherein the capacitor has a capacitance of approximately 15 pF.

17. The overvoltage protection device of claim 13 wherein the capacitor has a capacitance of approximately 15 pF.

18. The overvoltage protection device of claim 11 wherein the first PiN diode is larger than the third PiN diode and the second PiN diode is larger than the fourth PiN diode.

19. A method for fabricating an overvoltage protection device for an integrated circuit comprising the steps of:

providing a semiconductor substrate;

forming a plurality of PiN diodes on the semiconductor substrate;

coupling at least one of said PiN diodes to a signal node and to a positive voltage source; and

coupling at least one of said PiN diodes to a signal node and to a negative voltage source

wherein both PiN diodes are reverse biased when a voltage at the signal node is within a predetermined range and wherein at least one of said PiN diodes is forward biased when a voltage at the signal node is above a predetermined range and wherein at least one of said PiN diodes is forward biased when a voltage at the signal node is below a predetermined range.

20. The method of claim 19, wherein the semiconductor substrate is a high-resistivity silicon on insulator (SOI) semiconductor substrate

21. The method of claim 19, wherein the semiconductor substrate has a resistivity of approximately 1000 to 2000 ohm-cm P type, and wherein a top silicon layer of said semiconductor substrate is approximately 150 nm to 250 nm thick, and wherein a buried oxide layer is approximately 200 nm to 400 nm thick.

22. The method of claim 19, wherein each PiN diode of the plurality of PiN diodes has a PiN diode Periphery of approximately 50 μ

m.

23. The method of claim 19, wherein each PiN diode of the plurality of PiN diodes exhibits a capacitance in said reverse bias mode in the approximate range of 10 to 20 fF.

24. The method of claim 19, wherein each PiN diode of the plurality of PiN diodes exhibits a standardized capacitance in said reverse bias mode in the approximate range of 0.2 fF per micron of diode periphery.

25. The method of claim 19, wherein the steps of forming a PiN diode comprise the steps of:

forming an isolation region in a top silicon layer of the SOI semiconductor substrate;

depositing a spacer oxide to cover a center portion of the top silicon whereby the length of the spacer oxide defines an i region of the PiN diode;

masking the top silicon with a P+ implant photoresist mask;

implanting a P region of the top silicon with a P type doping agent;

masking the top silicon with a N+ implant photoresist mask; and

implanting a N region of the top silicon with a N type doping agent whereby the i region is sandwiched between the N region and the P region.