Capped dual metal gate transistors for CMOS process and method for making the same

• US 20040023478A1
• Filed: 07/31/2002
• Published: 02/05/2004
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Samavedam, Srikanth B., Tobin, Philip J.
• Granted Patent: US 6,894,353 B2
• Time in Patent Office: Days
• US Class Current: 438/592
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A first gate (120) and a second gate (122) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well (104) and a p-type well (106). In a preferred embodiment, first gate (120) includes a first metal layer (110) of titanium nitride on a gate dielectric (108), a second metal layer (114) of tantalum silicon nitride and a silicon containing layer (116) of polysilicon.. Second gate (122) includes second metal layer (114) of a tantalum silicon nitride layer on the gate dielectric (108) and a silicon containing layer (116) of polysilicon. First spacers (124) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers (124) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.

Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, wherein the second conductivity type is different than the first conductivity type;

forming a gate dielectric over the first and second wells;

forming a first metal layer over the gate dielectric;

removing a first portion of the first metal layer, wherein the first portion is over the second well;

after removing the first portion of the first metal layer, forming a second metal layer over the first and second wells, wherein the second metal layer is different than the first metal layer;

depositing a semiconductor layer comprising silicon over the second metal layer;

patterning the first metal layer, the second metal layer, and the semiconductor layer to form a first gate over the first well and a second gate over the second well;

forming first spacers adjacent the sidewalls of the first gate and the second gate; and

forming second spacers adjacent the first spacers.

2. The method of claim 1 further comprising forming an oxide liner between the first spacers and the second spacers.

3. The method of claim 1 wherein the first gate comprises the first metal layer and the second metal layer and the second gate comprises the second metal layer and not the first metal layer.

4. The method of claim 3 where the first and second metal layers have different work function.

5. The method of claim 1 further comprising:

forming an anti-reflective coating (ARC) over the semiconductor layer prior to patterning the first metal layer, the second metal layer and the semiconductor layer; and

removing the ARC prior to forming the first spacers.

6. The method of claim 1 wherein the semiconductor layer comprises polysilicon.

7. The method of claim 6 wherein the first metal layer comprises titanium nitride and formed by chemical vapor deposition.

8. The method of claim 7 wherein the second metal layer comprises tantalum.

9. A semiconductor device comprising:

a semiconductor substrate having a first well and a second well, wherein the first well has a first conductivity type and the second well has a second conductivity type different than the first conductivity type;

a gate dielectric over at least a portion of a first well and a portion of a second well;

a first gate stack over the first well and the gate dielectric, wherein the first gate stack comprises a first metal layer, a second metal layer, and a conductive silicon-containing layer, wherein the second metal layer is different from the first metal layer;

a second gate stack over the second well and the gate dielectric, wherein the second gate stack comprises the second metal layer and the conductive silicon-containing layer;

first spacers adjacent sidewalls of the first gate stack and the second gate stack; and

second spacers adjacent the first spacers.

10. The semiconductor device of claim 9, wherein the first spacers only partially cover sidewalls of the conductive silicon-containing layer of the first gate stack.

11. The semiconductor device of claim 9, wherein the first spacers are thinner than the second spacers.

12. The semiconductor device of claim 11, wherein the first spacers have a maximum thickness of approximately 50 to 200 angstroms.

13. The semiconductor device of claim 9, wherein one of the first metal layer and the second metal layer is selected from the group consisting of titanium nitride, iridium, platinum, tantalum silicon nitride, tantalum nitride, rhenium ruthenium oxide, molybdenum, ruthenium, iridium oxide, titanium, vanadium, zirconium, tantalum, aluminum, and niobium.

14. The semiconductor device of claim 9 wherein one of the first metal layer and the second metal layer is a material having a work function of approximately 4.6 to 5.5 eV and the other is a material having a work function of approximately 3.5 to 4.5 eV.

15. The semiconductor device of claim 9, wherein the first spacers and the second spacers are comprised of a nitride.

16. The semiconductor device of claim 9, further comprising an oxide liner between the first spacers and the second spacers.

17. The semiconductor device of claim 9, wherein the conductive silicon-containing layer is a material selected from the group consisting of silicon and silicon germanium.

18. The semiconductor device of claim 17, further comprising a silicide over the conductive silicon-containing layer of the first gate stack and the second gate stack.

19. A semiconductor device comprising:

a semiconductor substrate having a first well and a second well, wherein the first well has a first conductivity type and the second well has a second conductivity type different than the first conductivity type;

a gate dielectric over at least a portion of a first well and a portion of a second well;

a first gate over the first well and the gate dielectric and comprising a titanium nitride layer, a first tantalum silicon nitride layer, and a first conductive silicon-containing layer, wherein the titanium nitride layer is in physical contact with the gate dielectric; and

a second gate over the second well and the gate dielectric and comprising a tantalum silicon nitride layer and a conductive silicon-containing layer, wherein the tantalum silicon nitride layer of the second gate is in physical contact with the gate dielectric.

20. The semiconductor device of claim 19, further comprising first spacers adjacent sidewalls of the first gate and the second gate and second spacers adjacent the first spacers.

21. The semiconductor device of claim 20, wherein the first spacers expose a portion of the sidewalls of the conductive silicon-containing layer of the first gate.

22. The semiconductor device of claim 20, further comprising an oxide liner between the first spacers and the second spacers.

23. The semiconductor device of claim 20, wherein the first spacers are thinner than the second spacers.

24. The semiconductor device of claim 23, wherein the first spacers have a maximum thickness of approximately 50 to 200 angstroms.

25. The semiconductor device of claim 19, wherein the conductive silicon-containing layer is a material selected from the group consisting of silicon and silicon germanium.

26. The semiconductor device of claim 19, further comprising a silicide over the conductive silicon-containing layer in both the first gate and the second gate.

27. The semiconductor device of claim 19, wherein the first well is n-type and the second well is p-type.