Capped dual metal gate transistors for CMOS process and method for making the same

  • US 20040023478A1
  • Filed: 07/31/2002
  • Published: 02/05/2004
  • Est. Priority Date: 07/31/2002
  • Status: Active Grant
First Claim
Patent Images

1. A method for forming a semiconductor device, comprising:

  • providing a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, wherein the second conductivity type is different than the first conductivity type;

    forming a gate dielectric over the first and second wells;

    forming a first metal layer over the gate dielectric;

    removing a first portion of the first metal layer, wherein the first portion is over the second well;

    after removing the first portion of the first metal layer, forming a second metal layer over the first and second wells, wherein the second metal layer is different than the first metal layer;

    depositing a semiconductor layer comprising silicon over the second metal layer;

    patterning the first metal layer, the second metal layer, and the semiconductor layer to form a first gate over the first well and a second gate over the second well;

    forming first spacers adjacent the sidewalls of the first gate and the second gate; and

    forming second spacers adjacent the first spacers.

View all claims

    Thank you for your feedback