High performance system-on-chip passive device using post passivation process
First Claim
Patent Images
1. A post passivation system, comprising:
- a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point; and
a passive device, formed over said passivation layer and connected to said at least one top level metal contact point;
wherein said passivation opening'"'"'s width is larger than about 0.1 um.
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Abstract
A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
76 Citations
127 Claims
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1. A post passivation system, comprising:
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a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point; and
a passive device, formed over said passivation layer and connected to said at least one top level metal contact point;
wherein said passivation opening'"'"'s width is larger than about 0.1 um. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A post passivation system, comprising:
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a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
a passive device, formed over said passivation layer;
metal interconnections, formed of a same material as said passive device and formed over said passivation layer, and connected to at least one of said top level metal contact points;
wherein said passivation opening'"'"'s width is larger than about 0.1 um. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53)
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54. A post passivation system, comprising:
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a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
a passive device, formed over said passivation layer;
metal interconnections, formed of a different material than said passive device and formed over said passivation layer, and connected to at least one of said top level metal contact points;
wherein said passivation opening'"'"'s width is larger than about 0.1 um. - View Dependent Claims (55, 56, 57, 58)
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59. A method of forming a post passivation system, comprising:
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providing a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point; and
forming a passive device, formed over said passivation layer and connected to said at least one top level metal contact point;
wherein said at least one passivation opening is formed to a width larger than about 0.1 um. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 127)
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116. A method of forming a post passivation system, comprising:
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providing a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
forming a passive device over said passivation layer;
forming metal interconnections, formed of a same material as said passive device and formed over said passivation layer, and connected to at least one of said top level metal contact points;
wherein said passivation opening'"'"'s width is larger than about 0.1 um. - View Dependent Claims (117, 118, 119, 120, 121, 122)
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123. A method of forming a post passivation system, comprising:
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providing a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
forming a resistor over said passivation layer;
forming metal interconnections, formed of a different material as said resistor and formed over said passivation layer, and connected to at least one of said top level metal contact points;
wherein said passivation opening'"'"'s width is larger than about 0.1 um. - View Dependent Claims (124, 125, 126)
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Specification