High performance IP processor

• US 20040030757A1
• Filed: 06/10/2003
• Published: 02/12/2004
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Granted Patent: US 7,487,264 B2
• Time in Patent Office: Days
• US Class Current: 709/217
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol Layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.

Claims

1. An IP processor for enabling TCP or SCTP, or UDP, or other session oriented protocols over IP networks, said IP processor comprising:

a. at least one packet processor for processing IP packets;

b. a session memory for storing IP session information;

c. at least one memory controller for controlling memory accesses;

d. at least one media interface for coupling to at least one network; and

e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric.

2. The IP processor of claim 2 further comprising at least one of:

a. an IP Storage session memory for storing IP Storage session information;

b. a classification processor for classifying IP packets;

c. a flow controller for controlling data flow;

d. a policy processor for applying policies;

e. a security processor for performing security operations;

f. a packet memory for storing packets

g. a controller for control plane processing;

h. a packet scheduler;

i. a connection manager or session controller for managing sessions;

or

j. a combination of any of the foregoing.

3. In a hardware processor for transporting data packets in TCP/IP or other session oriented IP Protocol sessions or flows over an IP network, a scheduler for scheduling said packets to execution resources of the hardware processor, said scheduler comprising:

a. a resource allocation table for storing

i. the identification of at least some of said execution resources,

ii. the identification of the session which at least one of said resources is executing, and

iii. the processing state of said resources, and

b. a state controller and sequencer coupled to said resource allocation table and to said execution resources, said state controller and sequencer scheduling packets to be processed on a specific session to the execution resource executing said specific session, said scheduling based on at least the execution state of said execution resource.

4. The scheduler of claim 3 wherein said resource allocation table also stores the session on which at least some of said packets are to be processed.

5. The scheduler of claim 3 including a packet memory for storing a plurality of packets, said packet memory coupled to said state controller and sequencer.

6. In a data processing apparatus for transporting data packets in TCP/IP or other session oriented IP Protocol sessions or flows over an IP network, a scheduler for scheduling said packets to execution resources of the data processing apparatus, said scheduler comprising:

a. a resource allocation table for storing

i. the identification of at least some of said execution resources,

ii. the identification of the session which at least one of said resources is executing, and

iii. the processing state of said resources; and

b. a state controller and sequencer coupled to said resource allocation table, and to said execution resources, said state controller and sequencer scheduling packets to be processed on a specific session to the execution resource executing said specific session, said scheduling based on at least the execution state of said execution resource.

7. The scheduler of claim 6 wherein said resource allocation table also stores the session on which at least some of said packets are to be processed.

8. The scheduler of claim 6 further comprising a packet memory for storing a plurality of packets, said packet memory coupled to said state controller and sequencer.

9. A processor for processing Internet data packets in one or more sessions, and a session memory for storing session information for a plurality of said sessions.

10. The process, in a hardware implemented control plane processor or session controller coupled to a host processor or a remote peer, of creating new sessions and their corresponding session database entries responsive to new session connection requests received either from the host processor or the remote peer.

11. The process, in a hardware implemented control plane processor or session controller coupled to a host processor or a remote peer and including a TCP/IP hardware processor engine or an IP storage processor engine, or a combination of any of the foregoing, of tearing down or removing sessions and their corresponding session database entries responsive to session connection closure requests received either from the host processor or the remote peer or as a result of the operation by the said TCP/IP processor engine or IP Storage processor engine or a combination of any of the foregoing.

12. For use in a hardware implemented IP network application processor including an input queue and queue controller for accepting incoming data packets including new commands from multiple input ports and queuing them on an input packet queue for scheduling and further processing, the process comprising:

accepting incoming data packets from one or more input ports and queuing them on an input packet queue; and

de-queuing said packets for scheduling and further packet processing.

13. For use in a hardware implemented IP network application processor having one or more output queues for accepting outgoing data packets, including new commands, from one or more packet processor engines, TCP/IP processor engines or IP Storage processing engines, directing said packets on to an output port interface for sending them out to a network interface, said interface sending said packets on to the network, through one or more output packets, said process including:

accepting incoming data packets from one or more packet processing engines and queuing them on said output packet queue; and

de-queuing said packets for delivery to said output port based on the destination port information in said packet.

14. A hardware implemented IP network application processor for providing TCP/IP operations in sessions on information packets from or to an initiator and providing information packets to or from a target, comprising the combination of:

a. data processing resources including at least one programmable packet processor for processing said packets;

b. a TCP/IP session cache and memory controller for keeping track of the progress of, and memory useful in, said operations on said packets;

c. a host interface controller capable of controlling an interface to a host computer in an initiator or target computer system or a fabric interface controller capable of controlling an interface to a fabric; and

d. a media independent interface capable of controlling an interface to the network media in an initiator or target.

15. A hardware processor for enabling Internet Protocol packets or their payloads to stream from a network interface through said hardware processor to a host interface or a fabric interface during packet processing, said hardware processor comprising:

a. at least one packet processor for processing said packets;

b. a packet memory;

c. a scheduler coupled to said at least one packet processor and to said packet memory for scheduling said packets to said at least one packet processor;

d. a session memory for storing session information for those packets transmitted, encapsulated or encoded using a session oriented protocol; and

e. a session manager coupled to the foregoing elements for managing session states for those packets transmitted, encapsulated or encoded using a session oriented protocol.

16. The hardware processor of claim 15 further including a TCP processor engine for transporting the data in said packets or an IP Storage processor engine for storing the data in said packets.

17. The hardware processor of claim 15 wherein any of said elements a through e, or any parts thereof, are implemented in a single apparatus.

18. The hardware processor of claim 15 wherein any of said elements a through e or any of said processor engines, or parts thereof, are implemented in a single apparatus.

19. The hardware processor of claim 15 further including a processor for classifying said packets, a processor for applying a policy to said packets and a security processor for performing security functions for said packets.

20. The hardware processor of claim 19 wherein any of said processors for classifying, applying a policy or performing security functions, or parts thereof, are implemented in a single apparatus.

21. The hardware processor of claim 15 wherein said packet processor is a TCP/IP processor engine, or an IP Storage processor engine, or a packet processor engine with a packet oriented instruction set, or a packet processor engine with a RISC instruction set, or a combination of any of the foregoing.

22. An IP processor for enabling TCP or other session oriented protocols over IP networks, said processor comprising:

a. at least one packet processor for processing IP packets;

b. a session memory for storing IP session information;

c. at least one memory controller for controlling memory accesses;

d. at least one media interface for coupling to at lest one network; and

e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric;

i. wherein said processor operates in multiple stages, including one or more of the stages of (1) receiving incoming IP packets;

(2) providing security for said incoming IP packets;

(3) classifying said incoming IP packets;

(4) scheduling IP packets for processing;

(5) executing data processing operations on IP Packets;

(6) providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;

(7) transmitting IP packets onto a network;

(8) executing packet processing operations on data or commands forming IP packets; and

(9) providing security for outgoing IP packets, and

(a) each of said stages is capable of operating on different IP packets concurrently.

23. A TCP/IP processor implemented in hardware, said processor including a session memory for storing session information for a plurality of sessions.

24. A TCP/IP processor engine for processing Internet Protocol packets and comprising at least one of each of:

a. a checksum hardware for performing checksum operations;

b. a data memory for storing data used in the TCP/IP processor engine;

c. an instruction memory for storing instructions used in the TCP/IP processor engine;

d. an instruction fetch mechanism for fetching said instructions;

e. an instruction decoder for decoding said instructions;

f. an instruction sequencer for sequencing said instructions;

g. a session database memory for storing TCP/IP session data;

or

h. a session database memory controller for controlling said session database memory;

or a combination of any of the foregoing items a through i; and

a host interface, or a fabric interface, or bus controller, or memory controller or combination of any of the foregoing for coupling to host or a fabric.

26. A TCP/ IP processor for enabling TCP, SCTP, or UDP or other session oriented protocols, over IP networks, said processor comprising:

a. at least one TCP/IP processor engine for processing IP packets;

b. a session memory for storing session information;

c. at least one memory controller for controlling memory accesses;

d. at least one media interface for coupling to at lest one network; and

e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric.

27. The TCP/IP processor of claim 26 further comprising at least one of:

a. a packet processor engine for processing packets;

b. a classification processor for classifying IP packets;

c. a flow controller for controlling data flow;

d. a policy processor for applying policies;

e. a security processor for performing security operations;

f. a controller for control plane processing;

g. packet scheduler;

h. a packet memory for storing packets;

i. a connection manager or session controller for managing sessions;

or

j. a combination of any of the foregoing.

28. A host processor having a SCSI command layer and an iSCSI or IP Storage driver, said host processor capable of being coupled to a hardware implemented iSCSI or IP Storage controller useable in high speed storage over IP, said controller for transporting received iSCSI or IP Storage commands and PDUs, said controller having access to a data base for keeping track of data processing operations, said database being in memory on said controller, or in memory partly on said controller and partly in a computing apparatus other than said controller, said controller having a transmit and a receive path for data flow, said controller comprising:

a. a command scheduler for scheduling processing of commands, said scheduler coupled to said SCSI command layer and to said iSCSI or IP Storage driver;

b. a receive path for data flow of received data and a transmit path for data flow of transmitted data;

c. at least one transmit engine for transmitting iSCSI or IP Storage PDUs;

d. at least one transmit command engine for interpreting said PDUs and performing operations including retrieving information from said host processor using remote direct memory access and keeping command flow information in said database updated as said retrieving progresses;

e. at least one receive command engine; and

f. at least one receive engine for interpreting received commands into requests for at least one of said at least one receive command engine.

29. An IP storage processor implemented in hardware, said processor including a session memory for storing session information for a plurality of sessions.

30. An IP storage processor engine for processing Internet Protocol packets and comprising at least one of each of:

a. CRC hardware for performing CRC functions;

b. a data memory for storing data used in the processor engine;

c. an instruction memory for storing instructions used in the processor engine;

d. an instruction fetch mechanism for fetching said instructions;

e. an instruction decoder for decoding said instructions;

f. an instruction sequencer for sequencing said instructions;

g. an IP storage session database memory for storing IP storage session information;

h. an IP storage session database memory controller for controlling said IP storage session database memory;

i. combination of any of the foregoing items a through j; and

j. a host interface, or a fabric interface, or bus controller, or memory controller or combination thereof for coupling to a host or to a fabric.

31. The IP storage processor engine of claim 30 further comprising at least one of:

a. hash engine for performing hash operations;

b. a sequencer manager for sequencing operations;

c. a window operations manager for positioning packets within, and/or verifying received packets to be within, agreed windows;

d. a classification tag interpreter for interpreting classifications tags;

e. an out of order manager for handling out of order data;

f. a register file for storing data;

g. a PDU storage classifier for classifying packets into various attributes;

h. an IP storage state manager for managing IP storage session states;

i. a checksum component for performing checksum operations;

j. an execution resource unit or ALU for data processing;

k. an IP storage session database lookup engine for accessing session entries;

l. a SNACK engine for selective negative acknowledgment;

m. a SACK engine for selective positive acknowledgment;

n. a segmentation controller for controlling the segmentation of data;

o. a timer for event timing;

p. a packet memory for storing packets; and

q. a combination of any of the foregoing.

32. An IP Storage processor for enabling IP Storage protocols over IP networks, said processor comprising:

a. at least one IP Storage processor engine for processing IP storage packets;

b. an IP Storage session memory for storing session information;

c. at least one memory controller for controlling memory accesses;

d. at least one media interface for coupling to at least one network; and

e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric.

33. The IP Storage processor of claim 32 further comprising at least one of:

a. a packet processor engine for processing packets;

b. a classification processor for classifying IP packets;

c. a flow controller for controlling data flow;

d. a policy processor for applying policies;

e. a security processor for performing security operations;

f. a controller for control plane processing;

g. a packet scheduler;

h. a packet memory for storing packets;

or

i. a combination of any of the foregoing.

34. An IP processor capability for enabling TCP or other session oriented protocols over IP networks, said processor comprising:

a. at least one packet processor for processing IP packets;

b. a session memory for storing IP session information;

c. at least one memory controller for controlling memory accesses;

d. at least one media interface for coupling to at least one network; and

e. a host interface for coupling to at least one host or a fabric interface for coupling to a fabric;

i. wherein said processor operates in multiple stages, including one or more of the stages of (1) receiving incoming IP packets;

(2) providing security for processing said incoming IP packets if needed;

(3) classifying said incoming IP packets;

(4) scheduling IP packets for processing;

(5) executing data and/or processing operations on IP Packets;

(6) providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;

(7) executing protocol processing operations on data or commands forming IP packets;

(8) providing processing security for outgoing IP packets, if needed;

or (9) transmitting IP packets onto a network;

or any combination of the foregoing; and

ii. each of said stages is capable of operating on different IP packets concurrently.

35. The IP processor of claim 35 wherein each stage of said IP processor may take a different length of time to perform its function than one or more of the other stages of said IP processor.

36. A TCP/IP processor for enabling TCP over IP networks, said processor including a TCP/IP stack providing TCP/IP protocol termination and origination, said processor comprising:

a. At least one TCP/IP processor engine for processing IP packets;

b. A session memory for storing session information;

C. At least one memory controller for controlling memory accesses;

d. At least one media interface for coupling to at least one network; and

e. A host interface for coupling to at least one host or fabric interface for coupling to a fabric.

37. The TCP/IP processor of claim 36 further comprising at least one of:

a. A packet processor engine for processing packets;

b. A classification processor for classifying IP packets;

c. A flow controller for controlling data flow;

d. A policy processor for applying policies;

e. A security processor for performing security operations;

f. A controller for control plane processing;

g. A packet scheduler for scheduling packets;

h. A packet memory for storing packets;

i. A connection manager or session controller for managing TCP/IP sessions;

or

j. A combination of any of the foregoing.

42. The TCP/IP processor of claim 36 wherein said processor operates in multiple stages, including one or more stages of

a. Receiving incoming IP packets;

b. Providing security processing for said incoming IP packets if necessary;

c. Classifying said incoming IP packets;

d. Scheduling IP packets for processing;

e. Executing data and/or protocol processing operations on IP packets;

f. Providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;

g. Executing protocol processing operations on data or commands forming IP packets;

h. Providing security processing for outgoing IP packets if necessary;

i. Transmitting outgoing IP packets onto a network;

or

j. A combination of any of the foregoing; and

i. Each of said stages is capable of operating on different IP packets concurrently.

38. A TCP/IP processor for enabling TCP over IP networks, said processor including a TCP/IP stack providing TCP/IP protocol termination and origination, said stack providing an interface to sockets layer functions in a host processor to transport data traffic, said processor comprising:

a. At least one TCP/IP processor engine for processing IP packets;

b. A session memory for storing session information;

c. At least one memory controller for controlling memory accesses;

d. At least one media interface for coupling to at least one network; and

e. A host interface for coupling to at least one host or fabric interface for coupling to a fabric.

39. The TCP/IP processor of claim 38 further comprising at least one of:

a. A packet processor engine for processing packets;

b. A classification processor for classifying IP packets;

c. A flow controller for controlling data flow;

d. A policy processor for applying policies;

e. A security processor for performing security operations;

f. A controller for control plane processing;

g. A packet scheduler for scheduling packets;

h. A packet memory for storing packets;

i. A connection manager or session controller for managing TCP/IP sessions;

or

j. A combination of any of the foregoing.

43. The TCP/IP processor of claim 38 wherein said processor operates in multiple stages, including one or more stages of

a. Receiving incoming IP packets;

b. Providing security processing for said incoming IP packets if necessary;

c. Classifying said incoming IP packets;

d. Scheduling IP packets for processing;

e. Executing data and/or protocol processing operations on IP packets;

f. Providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;

g. Executing protocol processing operations on data or commands forming IP packets;

h. Providing security processing for outgoing IP packets if necessary;

i. Transmitting outgoing IP packets onto a network;

or

j. A combination of any of the foregoing; and

i. Each of said stages is capable of operating on different IP packets concurrently.

40. An IP Storage processor for enabling IP Storage protocols over IP networks, said processor including an IP Storage stack providing IP Storage protocol termination and origination, transporting information in active sessions over IP networks by transporting PDU'"'"'s specified by the IP storage standard said processor comprising:

a. At least one IP Storage processor engine for processing IP Storage packets;

b. An IP Storage session memory for storing session information;

c. At least one memory controller for controlling memory accesses;

d. At least one media interface for coupling to at least one network; and

e. A host interface for coupling to at least one host or fabric interface for coupling to a fabric.

25. The TCP/IP processor engine of claim 40 further comprising at least one of:

a. a hash engine for performing hash functions;

b. a sequencer manager for sequencing operations;

c. a window operations manager for performing windowing operations to position packets within, and/or verify packets to be within, agreed windows;

d. a classification tag interpreter for interpreting classification tags;

e. a frame controller for controlling data framing;

f. an out of order manager for handling out of order data;

g. a register file for storing data;

h. a TCP state manager for managing TCP session states;

i. a CRC component for performing CRC operations;

j. an execution resource unit or ALU for data processing;

k. a TCP session database lookup engine for accessing session entries;

l. an SNACK engine for selective negative acknowledgment;

m. an SACK engine for selective positive acknowledgment;

n. a segmentation controller for controlling the segmentation of data;

o. a timer for event timing;

p. a packet memory for storing packets; and

q. a combination of any of the foregoing.

41. The IP Storage processor of claim 40 further comprising at least one of:

a. A packet processor engine for processing packets;

b. A classification processor for classifying IP packets;

c. A flow controller for controlling data flow;

d. A policy processor for applying policies;

e. A security processor for performing security operations;

f. A controller for control plane processing;

g. A packet scheduler for scheduling packets;

h. A packet memory for storing packets;

or.

i. A combination of any of the foregoing.

44. The IP Storage processor of claim 40 wherein said processor operates in multiple stages, including one or more stages of

a. Receiving incoming IP Storage packets;

b. Providing security processing for said incoming IP Storage packets if necessary;

c. Classifying said incoming IP Storage packets;

d. Scheduling IP packets for processing;

e. Executing data and/or protocol processing operations on IP Storage packets;

f. Providing direct memory access for transferring data/packets to or from the memory of a system external to said processor;

g. Executing protocol processing operations on data or commands forming IP packets;

h. Providing security processing for outgoing IP Storage packets if necessary;

i. Transmitting outgoing IP packets onto a network;

or

j. A combination of any of the foregoing; and

i. Each of said stages is capable of operating on different IP Storage packets concurrently.