Memory device, circuits and methods for operating a memory device

• US 20040032759A1
• Filed: 08/14/2002
• Published: 02/19/2004
• Est. Priority Date: 08/14/2002
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Willassen, Trygve, Chow, David GenLong, Dahl, Hans Ola
• Granted Patent: US 6,920,060 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 29/026 in sense amplifiers

Abstract

A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.

Claims

1. A method of operating a memory device, comprising:

biasing the memory device from a power source;

determining data of the memory device; and

during at least a portion of the determining, decoupling the power source.

2. A method according to claim 1, in which the determining data comprises sensing a signal related to a condition of at least one memory cell of a plurality of memory cells of the memory device.

3. A method according to claim 1, in which the determining data comprises sensing a charge release from at least one ferroelectric memory cell of a plurality of ferroelectric memory cells of the memory device.

4. A method according to claim 1, in which the determining data comprises sensing a difference between a signal provided by at least one ferroelectric memory cell of the memory device relative to that of at least one reference ferroelectric cell of the memory device.

5. A method according to claim 4, in which the determining data further comprises:

biasing a first electrode of the at least one ferroelectric memory cell using a first voltage source;

biasing a first electrode of the at least one reference ferroelectric cell using the first voltage source; and

transitioning a voltage level of second electrodes of the at least one ferroelectric memory cell and the at least one reference ferroelectric cell to change their bias levels from quiescent levels to read levels;

the sensing comprises providing the sensing over a duration having an interval after the start of the transitioning of the voltage levels; and

the decoupling comprises electrically isolating the first voltage source from the first electrodes of respective ferroelectric memory and reference cells.

6. A method according to claim 5, in which the isolating the first voltage source is provided during the sensing the difference between the signals.

7. A method according to claim 6, in which the isolating the first voltage is maintained through the duration of the sensing the difference between the signals.

8. A method according to claim 5, in which the decoupling further comprises electrically isolating voltage sources associated with ferroelectric memory cells other than the at least one ferroelectric memory cell.

9. A method according to claim 1, in which

the biasing of the memory device comprises biasing a plurality of ferroelectric memory cells of the memory device with quiescent level voltages;

the determining data comprises;

biasing at least one select ferroelectric memory cell of the plurality with read level voltages; and

sensing charge released by the at least one select ferroelectric memory cell; and

the decoupling comprises decoupling at least one voltage source of voltage sources associated with the quiescent and the read level voltages.

10. A method according to claim 9, in which the biasing at least one select ferroelectric memory cell with the read level voltages comprises:

establishing from a first voltage source, a first voltage on a select bitline;

applying from a second voltage source, a second voltage to a select wordline that crosses the select bitline, and

establishing a magnitude of the second voltage relative the first voltage sufficient to affect a polarization state of the select ferroelectric memory cell between the select wordline and the select bitline; and

the decoupling comprises isolating the first voltage source from the select bitline during the sensing of released charge.

11. A method according to claim 10, the sensing of released charge comprising integrating charge propagated by the select bitline relative to that of a reference bitline.

12. A method according to claim 10, the decoupling further comprising isolating the second voltage source from the select wordline during the sensing.

13. A method according to claim 12, the decoupling further comprising electrically isolating wordlines other than the select wordline.

14. A method according to claim 13, the decoupling further comprising electrically isolating bitlines other than the select bitline.

15. A method of reading a ferroelectric memory device, comprising:

sensing a signal of a ferroelectric cell of the ferroelectric memory device; and

decoupling a power source associated with providing power to the ferroelectric memory device during at least a portion of the sensing.

16. A method according to claim 15, in which the decoupling the power source comprises increasing the source resistance of the power source.

17. A method according to claim 15, in which the decoupling the power source comprises adjusting the resistance of a controllable channel in series with a voltage source node associated with receiving a voltage to operate the memory device.

18. A method according to claim 15, in which the decoupling the power source comprises turning-off a gateable transistor having its channel electrically disposed in series with a voltage source node that is to receive power to power the memory device.

19. A method according to claim 15, in which the sensing comprises integrating charge propagated by an active bitline coupled to the ferroelectric memory cell;

and

the decoupling the power source includes electrically isolating the active bitline from the power source.

20. A method according to claim 15, in which the sensing comprises integrating a difference signal related to a difference between the charge propagated by an active bitline that is coupled to the ferroelectric memory cell and the charge propagated by a reference bitline that is coupled to a reference ferroelectric cell, the method further comprising:

precharging the active and reference bitlines with a reference bitline voltage of a bitline voltage source; and

isolating the reference and active bitlines from the bitline voltage source during the integrating.

21. A method according to claim 20, in which the isolating the reference and active bitlines comprises turning-off a transistor electrically disposed in series between the bitline voltage source and a node for sourcing at least the reference bitlines.

22. A method according to claim 20, in which the decoupling the power source comprises increasing the source resistance of the power source.

23. A method according to claim 22, in which the increasing the source resistance comprises turning-off at least one supply access transistor of the memory device that is electrically disposed in series between its power source and the respective circuit for driving at least one of the bitlines and wordlines of the ferroelectric memory device.

24. A method according to claim 23, further comprising starting the integrating after the turning-off of at least one supply access transistor.

25. A memory device comprising:

a memory cell;

a read circuit to read a state of the memory cell;

a supply node to receive power for operating the memory device;

a transistor comprising a controllable channel electrically disposed in series with the supply node and a control terminal to receive a control signal to affect the controllable channel; and

a controller responsive to a read request to establish a control signal for the transistor and to enable the read circuit to read the memory cell.

26. A memory device according to claim 25, in which the controller is responsive to the read request to turn-off the transistor during a portion of a read operation of the read circuit.

27. A memory device according to claim 25, in which the read circuit comprises a sense amplifier responsive to the controller to sense a charge release of the memory cell.

28. A memory device according to claim 27, in which the controller is operable responsive to the read request to turn-off the transistor and to enable the sense amplifier after turning-off the transistor.

29. A memory device according to claim 25, further comprising:

a plurality of bitlines, the memory cell coupled to an active bitline of the plurality;

a plurality of wordlines, the memory cell coupled to an active wordline of the plurality;

a wordline driver circuit to drive the active and other passive wordlines of the plurality with voltages of respective wordline voltage sources;

the transistor associated with a wordline voltage and having its controllable channel electrically disposed in series with the supply line between the wordline driver circuit and a supply node of one of the wordline voltage sources.

30. A memory device according to claim 29, further comprising a decoupling capacitor coupled to the supply line between the wordline driver circuit and the transistor.

31. A memory device according to claim 30, in which the memory cell comprises a

ferroelectric memory cell;

and

the memory device further comprises a bitline driver circuit to drive the active and other passive bitlines of the plurality with voltages of respective bitline voltage sources;

another transistor associated with a bitline voltage and comprising a controllable channel disposed in series with the supply line between the bitline driver circuit and a supply nodes of one of the bitline voltage sources.

32. A memory device according to claim 31, further comprising a decoupling capacitor coupled to the supply line between the bitline driver circuit and the another transistor

33. A memory device according to claim 31, in which the bitline driver circuit comprises a buffer to buffer a bitline reference voltage for availability to the bitlines, the buffer to be powered from a source separate from the bias sources for the wordlines and bitlines.

34. A memory device according to claim 31, further comprising a bitline multiplexer configurable responsive to the controller to couple the active bitline of the plurality to receive the reference voltage of the buffer.

35. A memory device according to claim 34, in which the buffer input is coupled to a reference bitline of the plurality of bitlines.

36. A memory device according to claim 30, in which the capacitor comprises at least one of a semiconductor dopant well and an insulated gate of a MOSFET.

37. A ferroelectric memory device comprising:

a plurality of bitlines;

a sense amplifier to sense a signal of a select bitline of the plurality relative to that of a reference bitline of the plurality;

an amplifier to source the sense amplifier with a reference signal representative of that of the reference bitline; and

a read controller responsive to a read request to isolate the reference bitline from the voltage source.

38. A device according to claim 37, further comprising:

a plurality of wordlines;

an active wordline of the plurality crossing the active bitline and the reference bitline with ferroelectric material therebetween;

a first voltage source to provide a read level voltage for biasing the active wordline; and

a second voltage source to provide a quiescent level voltage for biasing wordlines of the plurality other than the active wordline;

at least one of the first and second voltage sources comprising a supply switch electrically disposed in the serial path associated with the supply of respective read level or quiescent level voltages.

39. A device according to claim 38, in which the at least one of the first and second voltage sources further comprises a capacitor electrically coupled to the serial path on a side of the supply switch opposite the supply.

40. A device according to claim 39, in which the capacitor comprises at least one of a doped-well in a semiconductor substrate and insulated gate of a drain-source shorted MOSFET formed within the semiconductor substrate.

41. A device according to claim 40, in which the plurality of wordlines and bitlines of the ferroelectric memory device form an array of ferroelectric memory cells, the array of ferroelectric memory cells disposed over at least a portion of the doped-well of the semiconductor substrate.

42. A device according to claim 41, in which the supply switch is disposed on the semiconductor substrate.

43. A device according to claim 38, in which

the supply switch comprises at least one MOSFET having its channel disposed between the plurality of wordlines and the supply;

and

the read controller to drive the gate of the at least one MOSFET responsive to the read request.

44. A device according to claim 38, in which

the supply switch comprises first and second MOSFETs having channels coupled in parallel with each other, the parallel channels together within the serial path to the supply;

and

the read controller to drive the gates of the first and second MOSFETs separately.

45. A device according to claim 37, in which the switch comprises a MOSFET having its channel electrically disposed in series with an electrical path between the reference bitline and the reference voltage source.

46. A module comprising:

a substrate; and

at least one memory chip disposed on the substrate;

a supply pad on the substrate to couple a power source;

an internal node on the substrate to channel power to the at least one memory chip; and

a controllable channel disposed between the supply pad and the internal node.

47. A module according to claim 46, further comprising a control circuit to control the controllable channel.

48. A module according to claim 46, further comprising a capacitor coupled to the internal node.

49. A module according to claim 48, in which the capacitor comprises a first dopant-type well in a second dopant-type region of the substrate, the second dopant type opposite the first.

50. A module according to claim 49, in which the at least one memory chip comprises a ferroelectric memory disposed over at least a portion of the well.

51. A module according to claim 48, in which the capacitor comprises an N-well in a P-type region of the base substrate.

52. A module according to claim 46, in which the controllable channel comprises a switch.

53. A module according to claim 46, in which

the controllable channel comprises a MOSFET having its channel electrically disposed between the supply pad and the internal node;

and

the memory module further comprises a controller to drive the gate of the MOSFET responsive to a read request.

54. A module according to claim 53, in which

the controllable channel further comprises a second MOSFET having its channel electrically disposed between the supply pad and the internal node in parallel with the first MOSFET;

and

the controller is to drive the gate of the second MOSFET separately from that of the first MOSFET.

55. A module according to claim 54, further comprising a capacitor coupled to the internal node.

56. A data processing system comprising:

a processor;

a bus coupled to the processor;

a ferroelectric memory coupled to the bus, the memory to provide data responsive to a read request;

supplies to power the memory; and

isolation circuitry to isolate the ferroelectric memory from at least one supply of the supplies responsive to an isolation request.

57. A data processing system according to claim 56, further comprising a read controller to provide an isolation request to the isolation circuitry during a read of the ferroelectric memory.

58. A data processing system according to claim 56, in which the isolation circuitry comprises a transistor electrically disposed between the ferroelectric memory and the at least one voltage supply.

59. A data processing system according to claim 58, in which the isolation circuitry further comprises a decoupling capacitor electrically coupled to a supply node between the transistor and the memory.

60. A data processing system according to claim 58, further comprising:

a read controller to establish a resistance of the transistor responsive to a read request of the ferroelectric memory.

61. A method of sensing, comprising:

integrating, over a first duration, a first signal provided by a material responsive to a first stimulus and obtaining a first integrated signal;

integrating, over a second duration, a second signal provided by the material responsive to a second stimulus and obtaining a second integrated signal, the second stimulus related to the first stimulus;

determining a condition of the material based upon the first and the second integrated signals; and

establishing a length of time for at least one of the first and the second durations dependent upon an amount of charge released by the material.

62. A method according to claim 61, further comprising:

preparing a read voltage for the first and second stimuli; and

preparing a memory cell of a memory device to receive the read voltage;

the integrating over the first duration and the integrating over the second durations each comprises integrating an output signal of the memory cell responsive to application of the read voltage to the memory cell.

63. A method according to claim 62, in which the memory cell comprises a ferroelectric cell and the integrations each comprise integrating a charge release of the ferroelectric cell during application of the read voltage.

64. A method according to claim 63, further comprising:

selecting a bitline coupled to the ferroelectric cell;

the integrations each comprising integrating a signal of the bitline.

65. A method according to claim 64, further comprising:

selecting a wordline coupled to the ferroelectric cell; and

applying the read voltage to the selected wordline;

the integrations occurring during the applying of the read voltage to the wordline.

66. A method according to claim 65, in which the integrating the signal of the selected bitline comprises:

integrating a difference between a signal of the selected bitline relative to a signal of a reference bitline.

67. A method according to claim 66, further comprising, before each of the integrations, biasing the reference and selected bitlines with a bitline offset voltage.

68. A method according to claim 67, in which the read voltage is defined with a magnitude relative to the bitline offset voltage and sufficient to set a polarization of the ferroelectric cell.

69. A method according to claim 66, in which the establishing a length of time comprises:

comparing a signal of the reference bitlines to a threshold signal; and

fixing the length of time dependent upon the comparing.

70. A method according to claim 69, in which the establishing further comprises:

stopping at least one of the first and the second integrations when the comparing determines that the level of the signal of the reference bitline has reached the level of the threshold signal.

71. A method according to claim 69, in which the establishing a length of time comprises:

sampling the signal of the reference bitline; and

using the level of the sample to establish the threshold signal for the comprising.

72. A method according to claim 71, in which the establishing further comprises:

establishing a fixed time for the first duration; and

taking the sampling at the end of the first duration.

73. A method of reading a ferroelectric memory, comprising:

driving a wordline with a read signal;

integrating a signal of a data bitline; and

affecting the integrating based upon a signal of a reference bitline.

74. A method of reading a ferroelectric memory according to claim 73, in which:

the integrating comprises performing first and second integrations of the signal of the data bitline; and

the affecting comprises;

obtaining a sample of the signal of the reference bitline at the end of the first integration; and

setting a duration for the second integration dependent upon the level of the sample obtained from the referenced bitline at the end of the first integration.

75. A method of reading a ferroelectric memory according to claim 73, in which:

the integrating comprises performing first and second integrations of the signal of the data bitline; and

the affecting comprises;

comparing the signal of the reference bitline to a threshold level; and

setting the durations of at least one of the first and second integrations dependent upon the comparing.

76. A method of reading a ferroelectric memory according to claim 75, in which the affecting comprises setting the duration of both the first and second integration dependent on the comparing.

77. A method of reading a ferroelectric memory according to claim 76, further comprising:

sampling the signal of the reference bitline at the conclusion of the first integration; and

using the level of the sampling as the threshold level for the comparing during the second integration;

the second integration stopped when the signal of the reference bitline reaches the threshold level.

78. A method of reading a ferroelectric memory according to claim 76, further comprising:

obtaining a first sample of the integrated signal obtained during the first integration of the data bitline;

determining a data value dependent upon a level of the first sample and a level of the integrated signal obtained during the second integration.

79. A method of reading a ferroelectric memory according to claim 78, in which the determining comprises:

determining a difference between the level of the integrated signal of the second integration and that of the first sample; and

using as the basis for establishing the data values, the determined difference.

80. A method of reading a ferroelectric memory according to claim 78, in which the determining comprises:

subtracting the first sample obtained from the integrated signal of the first integration from the integrated signal of the second integration;

comparing a result of the subtraction to a predetermined threshold; and

establishing a data value based upon the comparison.

81. A method of reading a ferroelectric memory according to claim 75, in which the driving the wordline with the read signal comprises:

activating the wordline with a read level voltage, the read level voltage of a magnitude relative that of the bitline to set a dielectric polarization of ferroelectric material electrically therebetween.

82. A method of reading a ferroelectric memory according to claim 81, further comprising biasing at least one of the data bitlines, reference bitline and wordline with quiescent levels during a reset interval between the first and second integrations.

83. A method of reading a ferroelectric memory according to claim 81, in which the activation of the wordline with the read level voltage occurs after starting the first integration.

84. A method of reading a ferroelectric memory according to claim 75, in which the integrating integrates a difference between a signal of the date bitline relative to a signal of the reference bitline.

85. A device comprising:

a memory cell;

a signal line to carry a signal of the memory cell;

a sense amplifier to determine a data value of the memory cell dependent upon signals of the signal line, the sense amplifier comprising;

an integrator to integrate a signal of the signal line; and

a sampling comparator comprising a first portion operable to sample signals of the integrator;

the sampling comparator further comprising a second portion operable to resolve a data value dependent upon a signal from the integrator and a sample previously obtained by the first portion.

86. A device of claim 85, the controller operable to:

enable the integrator to perform at least two integrations;

enable the sampling comparator to sample the signal of the integrator at the end of a duration of the first integration; and

enable the sampling comparator to resolve a data value at the end of a duration of the second integration.

87. A device of claim 86, further comprising:

a reference circuit to establish a signal to emulate a signal of the signal line; and

a timer to establish the durations of the first and second integrations;

the timer to affect at least one of the durations dependent upon the signal established by the reference circuit.

88. A device of claim 87, in which the memory cell comprises a select ferroelectric memory cell;

the memory device further comprising a plurality of other ferroelectric memory cells;

the signal line coupled, as a bitline, to the select ferroelectric memory cell and to some of the other ferroelectric memory cells; and

the reference circuit to establish a signal to emulate a sneak current of the bitline.

89. A device of claim 87, in which the reference circuit comprises a reference bitline;

and

the timer comprises a comparison circuit to receive a signal of the reference bitline and indicate when the level of the signal of the reference bitline has reached a predetermined threshold;

the timer responsive to an indication of the comparison circuit to stop a duration of at least one of the first and second integrations.

90. A device according to claim 87, in which the reference circuit comprises a reference bitline;

and

the timer comprises;

a sampler operable to obtain a sample of a signal of the reference bitline for use as a threshold; and

a comparator operable to indicate when a level of the signal of the reference bitline has reached the threshold.

91. A device according to claim 90, the timer operable to fix a time for the first duration of the first integration;

the sampler of the reference circuit to sample the signal of the reference bitline at the end of the first duration; and

the timer to stop the second duration dependent upon an indication of the comparator.

92. A data processing system comprising:

a bus;

a processor coupled to the bus;

a ferroelectric memory coupled to the bus, comprising;

a bitline;

at reference bitline;

ferroelectric memory cells coupled to the bitlines;

a sense amplifier to determine a data value of a memory cell dependent upon signals of the bitlines;

the sense amplifier comprising;

an integrator to integrate a signal of the bitline relative to a signal of the reference bit line; and

a sampling comparator comprising a first portion operable to sample a signal of the integrator;

the sampling comparator further comprising a second portion operable to determine a data value dependent upon a signal of the integrator and a sample previously obtained.

93. A data processing system according to claim 92, further comprising a timer to establish durations for first and second integrations of the integrator;

the timer to affect at least one of the durations dependent upon a level of the signal of the reference bitline.

94. A data processing system according to claim 93, in which the timer comprises:

a sampler operable to obtain a sample of the signal of the reference bitline for use as a threshold; and

a comparator operable to indicate when a level of the signal of the reference bitline reaches the threshold.

95. A data processing system according to claim 94, the timer operable to fix a time for the duration of the first integration;

the sampler of the reference circuit to sample the signal of the reference bitline at the end of the first duration; and

the timer to stop the duration of the second integration dependent upon the comparator indicating that the level of the signal of the reference bitline has reached the threshold.

96. A data processing system according to claim 95, further comprising a reset circuit to bias at least one of the bitlines, including the reference bitline, with a quiescent level voltage during an interval of time between the first and second integrations.

97. A device comprising:

a bitline;

an integrator to integrate a signal of a bitline; and

a self-timer circuit to influence a duration of an integration of the integrator dependent upon a reference signal.

98. A device according to claim 97, further comprising:

a memory cell coupled to the bitline;

the integrator operable to integrate a signal of the memory cell propagated by the bitline; and

a reference bitline coupled in a reference cell;

the self-timer operable to affect the duration of the integration dependent upon the level of a signal of the reference bitline.

99. A device according to claim 98, the integrator operable to integrate a difference signal representative of the level of a signal of the bitline defined relative to that of the reference bitline.

100. A device according to claim 98, further comprising:

a sampler to obtain a sample of a signal of an output of the integrator following a first duration; and

a comparator operable to compare a sample of the sampler to the signal of the integrator'"'"'s output.

101. A device according to claim 100, further comprising a latch operable to establish a data value dependent upon the output of the comparator.

102. A device according to claim 101, the self timer operable to:

enable the latch at the end of a second duration;

the self-timer establishing the end for the second duration dependent upon the level of the signal of the reference bitline.

103. A device according to claim 102, the self-timer comprising:

a sampler operable to obtain a sample of the signal of the reference bitline at the end of the first duration; and

a comparator operable to signal an end for the second duration when the level of the signal of the reference bitline reaches the level of a sample of the sampler.

104. A device according to claim 102, the self-timer further comprising:

a threshold source; and

a comparator operable to signal the end of at least one of the first and second durations dependent upon the level of the signal of the reference bitline and the level of the signal of the threshold source.

105. A device according to claim 104, in which the comparator comprises:

a first input to receive the signal of the reference bitline; and

a second input to receive a second signal;

the threshold source disposed to affect at least one of the signal of the reference bitline or the level of the second signal as presented to their respective first and second inputs of the comparator.

106. A memory device comprising:

a bitline;

a reference bitline;

a first correlated-double sampler operable to obtain samples of a signal of the bitline and a signal of the reference bitline; and

a first comparator operable to establish an output signal based upon the signal of the bitline and the samples of the first correlated-double sampler.

107. A memory device according to claim 106, further comprising:

a wordline that overlaps the bitline and reference bitline;

a controller operable to activate the wordline with a read level voltage; and

a timer-circuit operable to enable the first correlated-double sampler to obtain the samples after a first activation of the wordline.

108. A memory device according to claim 107, further comprising:

an integrator disposed between the bitline and the first correlated-double-sampler;

the integrator to integrate a signal of the bitline; and

the first correlated-double-sampler to sample a signal of the integrator.

109. A memory device according to claim 108, the integrator to integrate a difference between the level of the signal of the bitline defined relative to the level of the signal of the reference bitline.

110. A memory device according to claim 107, further comprising:

a latch operable under the control of the timer circuit to determine and latch a data value dependent upon the output signal of the first comparator;

the timer circuit further operable to enable the latch after a second activation of the wordline.

111. A memory device according to claim 110, in which the controller is operable to enable the second activation of the wordline after the first activation.

112. A memory device according to claim 106, further comprising:

a threshold source disposed in a signal path between the bitline and the first correlated-double-sampler to introduce an offset voltage therebetween;

the threshold source adjustable to affect the offset voltage; and

a controller operable to enable operation of the threshold source for at least a portion of time during operation of the first comparator.

113. A memory device according to claim 112, further comprising:

a latch configurable under the control of the controller to determine and latch a data value based upon the level of the signal of the first comparator;

the controller to enable operation of the latch.

114. A memory device according to claim 113, further comprising:

a timer circuit operable to establish when the first correlated-double-sampler will obtain the samples;

the timer circuit further operable to trigger the controller to enable the latch.

115. A memory device according to claim 112, further comprising:

a second comparator operable to signal when the level of a signal of the reference bitline reaches a threshold level;

a latch configurable to determine and latch a data value based upon the level of the output signal of the first comparator; and

a controller operable to enable the latch responsive to the signal of the second comparator.

116. A memory device according to claim 115, further comprising:

a threshold source operable under control of the controller to source a threshold signal;

the second comparator to receive the threshold signal as the threshold level.

117. A memory device according to claim 116, the controller further operable to control when the threshold source is to provide the threshold signal to the second comparator;

and

the controller further operable to trigger the correlated-double-sampler to obtain the samples responsive to the signaling of the second comparator.

118. A memory device according to claim 112, further comprising:

a second correlated-double-sampler operable under the control of the controller to obtain a sample of the signal of the reference bitline and that of an offset signal;

the controller operative to enable the second correlated-double-sampler to sample responsive to conclusion of a fixed first duration; and

the controller further operative upon starting a second duration after the first duration, to enable samples of the second correlated-double-sampler to be used as timer reference levels; and

a second comparator operable to signal conclusion of the second duration dependent upon the level of the signal of the reference bitline, the level of the offset signal and the timer reference levels of the samples of the second correlated□

double sampler.

119. A memory device according to claim 118, further comprising:

a latch operable to receive signals of the first comparator;

the controller further operable responsive to conclusion of the first duration to enable the first correlated-double-sampler to obtain samples of the signal of the bitline and the signal of the reference bitline; and

the controller further operable responsive to conclusion of the second duration to enable the latch.

120. A memory device according to claim 119, further comprising:

an integrator disposed between the bitline and the first correlated-double sampler;

the integrator operable under the control of the controller to integrate a signal of the bitline relative to a signal of the reference bitline.

121. A memory device according to claim 120, the controller operable to enable the

integrator during the first and the second durations;

and

the correlated-double-sampler operable under the control of the controller to obtain a sample of the integrated signal as the sample of the signal of the bitline.

122. A device comprising:

a memory cell;

a reference cell; and

a sense amplifier for sensing signals of the memory cell relative to the reference cell, the sense amplifier comprising;

a differential amplifier having differential inputs and differential outputs;

a first capacitor disposed in series with one of the differential inputs, the first capacitor to receive a signal of the memory cell;

a second capacitor disposed in series with the other of the differential inputs;

the second capacitor to receive a signal of the reference cell; and

switches configurable to short the differential inputs of the differential amplifier to respective other ones of the differential outputs.

123. A device according to claim 122, further comprising:

an integrator electrically disposed between the differential amplifier and memory cell;

the integrator operable to integrate a signal of the memory cell relative to a signal of the reference cell; and

the integrator comprising an output to drive the first capacitor with the integrated signal.

124. A device according to claim 122, further comprising a threshold source selectably operable to affect the level of a signal received by one of the first and second capacitors.

125. A device according to claim 124, further comprising:

a timing controller to establish a duration for a first integration of the integrator and a duration for a second integration of the integrator;

the timing controller operable to close the switches during the first duration and to open the switches during the second duration.

126. A device according to claim 125, further comprising:

a latch operable under the control of the timing controller to receive an output from the sense amplifier;

the timing controller operable, responsive to conclusion of the duration of the second integrations, to enable the latch.

127. A device according to claim 126, the timing controller to control operation of the threshold source.

128. A device according to claim 122, further comprising a timing circuit to control operation of the switches.

129. A device according to claim 128, the timing circuit comprising a comparator to effect conclusion of a sense interval dependent upon a signal of the reference cell.

130. A device according to claim 129, the timing circuit further comprising:

a sampler to obtain a sample representative of a signal of the reference cell at a conclusion of a first sense interval; and

a controller operable to configure the comparator to effect conclusion of a second sense interval based upon a signal of the reference cell and a sample of the sampler.

131. A device according to claim 129, timing circuit further comprising:

an adjustable threshold source;

the comparator operable to compare a signal of the reference cell to a signal of the adjustable threshold source; and

the comparator further operable to signal conclusion for sense intervals responsive to the comparator.

132. A method of sensing comprising:

driving a wordline with a read level voltage;

sampling a signal of a bitline after a first duration of driving the wordline; and

after conclusion of a second duration of driving the wordline, determining a data value dependent upon a signal of the bitline and a previous sampling thereof.

133. A method of sensing according to claim 132, further comprising:

sampling a signal of a reference bitline after the first duration;

the determining, after the conclusion of the second duration, further dependent upon a signal of the reference bitline and a previous sampling thereof.

134. A method of sensing according to claim 133, in which the determining comprises:

subtracting the sample of the reference signal from the reference signal to obtain a first difference signal;

subtracting the sample of the bitline signal from the bitline signal to obtain a second difference signal;

comparing the first difference signal to the second difference signal; and

establishing the data value based upon the comparison.

135. A method of sensing according to claim 134, further comprising adjusting one of the first and second difference signal with a threshold offset.

136. A method of sensing according to claim 132, further comprising:

integrating a signal of the bitline; and

using the integrated signal of the bitline as the signal of the bitline.

137. A method of sensing according to claim 136, further comprising:

biasing the bitline with a bitline offset voltage during a reset duration between the first and the second durations; and

clearing the integrated signal during the reset duration.

138. A method of sensing according to claim 136, in which the integrating comprises integrating a difference between the signal of the bitline and a signal of a reference bitline.

139. A method of sensing according to claim 138, further comprising:

comparing a voltage of the reference bitline to a self-timer threshold voltage; and

establishing a length of time for at least one of the first and second durations dependent upon the comparing.

140. A method comprising:

conditioning domains of the polarizable material of the plurality of memory cells, the conditioning comprising;

applying a first signal to polarizable material between at least one wordline and at least one bitline to establish a first polarization of the polarizable material; and

applying a second signal to the polarizable material between the at least one wordline and the at least one bitline to establish a second polarization thereof opposite the first.

141. A method according to claim 140, further comprising sequentially and repetitively repeating the applying the first signal and the applying the second signal.

142. A method according to claim 140, further comprising:

forming a plurality of memory cells with ferroelectric material between a plurality of bitlines and a plurality of wordlines;

the applying the first signal comprises apply a first voltage to the at least one bitline of the plurality relative to the at least one wordline of the plurality to establish a first electric field and to set a polarization of the domains of the ferroelectric material therebetween; and

the applying the second signal comprises applying a second voltage to the bitline relative to the wordline to establish a second electric field, of polarity opposite the first electric field, and to reverse a polarization of the domains of the ferroelectric material.

143. A method according to claim 140, in which

the forming a plurality of memory cells comprises forming ferroelectric material between the plurality of bitlines and the plurality of wordlines;

the conditioning comprises repetitively and sequentially writing the ferroelectric cells with one/zero data followed by writing the ferroelectric cells with zero/one data.

144. A method according to claim 143, in which the forming a plurality of memory cells further comprises forming reference cells coupled to a reference bitline of the plurality;

and

the conditioning further comprises;

writing at least one reference cell of the reference bitline with data of a control register;

changing the data of the control register; and

after the changing of the data of the control register, again writing the at least one reference cell with the data of the control register.

145. A method according to claim 144, in which the writing comprises:

driving the reference bitline with a signal related to the data of the control register; and

biasing at least one wordline that crosses the reference bitline with a first-level voltage.

146. A method according to claim 145, in which the driving the bitline comprises driving the bitline with either a switching-level voltage when the data of the control register comprises one of a “

1”

or “

0”

, or a quiescent-level voltage when the data of the control register comprises the other of a “

1”

or “

0”

;

the switching-level and quiescent-level voltages defined relative to the first-level voltage for biasing the at least one wordline.

147. A method according to claim 144, further comprising:

reading data of the reference cells of the reference bitline;

comparing the data read from the reference cells to that previously written therein; and

determining operability of the reference bitline based upon the comparing.

148. A method of testing a ferroelectric memory device, comprising:

electrically coupling a reference bitline to a sense amplifier in place of an active bitline; and

sensing a signal of the reference bitline with the sense amplifier.

149. A method according to claim 148, further comprising:

identifying the sense amplifier associated with sensing data of ferroelectric cells coupled to the active bitline of the memory device; and

identifying the reference bitline of the memory device configurable to provide a reference signal to the sense amplifier;

the sense amplifier operable to compare a signal of the active bitline to that of the reference bitline when sensing of data of a ferroelectric memory cell of the active bitline.

150. A method according to claim 149, further comprising:

charging the reference bitline with a first voltage level before the sensing the signal of the reference bitline; and

comparing the signal as sensed from the reference bitline with the first voltage level.

151. A method according to claim 148, in which:

the electrically coupling comprises swapping the reference bitline with the active bitline as coupled to the sense amplifier; and

the sensing the signal of the reference bitline is performed as a part of reading data of a reference ferroelectric cell coupled to the reference bitline.

152. A method according to claim 148, further comprising:

determining an operability of the reference bitline based upon the signal that is sensed on the reference bitline.

153. A method according to claim 148, further comprising:

electrically coupling the active bitline to the sense amplifier in place of the reference bitline;

writing data to reference cells coupled to the reference bitline;

reading data of the reference cells with the sense amplifier; and

comparing the data read to that written.

154. A method according to claim 153, further comprising determining operability of the reference bitline based upon the comparing.

155. A method according to claim 148, further comprising:

before the sensing the signal of the reference bitline, biasing the reference bitline with a first voltage level;

the sensing the signal of the reference bitline comprising sensing a difference between a signal of the reference bitline relative to a signal of the active bitline.

156. A method according to claim 155, in which the sensing comprises integrating the difference between the signal of the reference bitline relative to that of the active bitline.

157. A method according to claim 156, further comprising:

storing 0/1 data into a reference ferroelectric memory cell coupled to the reference bitline; and

storing 1/0 data into an active ferroelectric memory cell coupled to the active bitline;

the sensing performed after the storing the data into the active and the reference ferroelectric memory cells and as a part of reading data of the reference ferroelectric memory cell.

158. A memory device, comprising:

a bitline coupled to a first column of ferroelectric memory cells;

a reference bitline coupled to a second column of ferroelectric memory cells;

a sense amplifier to sense a difference between charge propagated by the bitline relative to the reference bitline; and

a switching circuit selectively configurable to swap the bitline and the reference bitline couplings to the sense amplifier.

159. A memory device according to claim 158, in which the switching-circuit comprises:

a first multiplexer to select one of the bitline and reference bitline to be electrically coupled to a first input of the sense amplifier; and

a second multiplexer to select the other one of the bitline and the reference bitline to be coupled to a second input of the sense amplifier; and

the sense amplifier to output a signal based upon a difference between signals at its first and second inputs.

160. A memory device according to claim 159, in which the sense amplifier comprises an integrator to establish its output signal by integrating the difference between the signals at the first and second inputs.

161. A memory device according to claim 160, further comprising a multiplexer to select the reference bitline from amongst a plurality of available reference bitlines of respective columns of ferroelectric memory cells of the memory device.

162. A memory device according to claim 161, further comprising a multiplexer to select the bitline from amongst a plurality of available bitlines of respective columns of ferroelectric memory cells of the memory device.

163. A memory device according to claim 162, further comprising a controller to establish a control signal for configuring the multiplexer to select a particular bitline of the plurality;

the control signal to also configure the multiplexer associated with the plurality of reference bitlines to select a particular reference bitline of the plurality.

164. A semiconductor die having a memory device thereon, the memory device comprising:

a plurality of bitlines, the plurality of bitlines comprising at least one reference bitline;

a plurality of wordlines crossing the plurality of bitlines;

ferroelectric material disposed between the plurality of bitlines and the plurality of wordlines;

read circuitry to determine data of a memory cell coupled to a data bitline of the plurality;

the read circuitry to determine the data by comparing a signal propagated by the data bitline relative to a reference signal propagated by the reference bitline; and

switches electrically disposed between the data bitline, reference bitline and read circuitry, the switches selectably operable to electrically couple the reference bitline to the read circuitry in place of the data bitline.

165. A semiconductor die according to claim 164, in which the switches comprise a multiplexer to select one of the data bitline and reference bitline to be electrically coupled to a data input of the read circuitry to provide a data signal to the read circuitry.

166. A semiconductor die according to claim 165, in which the switches further comprise another multiplexer to select the other of the data bitline and reference bitline to be electrically coupled to a reference input of the read circuitry to provide a reference signal to the read circuitry.

167. A semiconductor die according to claim 166, in which the read circuitry comprises an integrating-amplifier to integrate the difference between a signal at one of the data input and reference input relative to a signal at the other.