Pulse width modulated spatial light modulators with offset pulses

• US 20040036707A1
• Filed: 08/21/2002
• Published: 02/26/2004
• Est. Priority Date: 08/21/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Willis, Thomas E.
• Granted Patent: US 7,317,464 B2
• Time in Patent Office: Days
• US Class Current: 345/691
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607

Abstract

In some embodiments, a display system includes a spatial light modulator including at least one pixel, a pixel source including pixel data corresponding to the pixel, a memory circuit connected to the pixel source and configured to store a pixel value corresponding to the pixel data, a pulse width modulation circuit connected between the memory circuit and the spatial light modulator, the pulse width modulation circuit adapted to generate a pulse to drive the pixel of the spatial light modulator, wherein a duration of the pulse corresponds to the pixel value and wherein the pulse is offset with respect to a start time and an end time of a refresh cycle of the spatial light modulator, and a control circuit connected to at least one of the memory circuit, the spatial light modulator, and the pulse width modulation circuit. Other embodiments are described and claimed.

Claims

1. A method of pulse width modulating a pixel of a spatial light modulator, comprising:

reading a pixel value from a pixel source;

offsetting an active time of a signal with respect to a start time and an end time of a refresh cycle, wherein a duration of the offset signal corresponds to the pixel value; and

driving the pixel of the spatial light modulator with the offset signal.

2. The method as recited in claim 1, wherein the offset signal is centered with respect to the refresh cycle.

3. The method as recited in claim 1, wherein the spatial light modulator is illuminated by a light engine and wherein an amount of time the offset signal is offset is in accordance with an operating characteristic of the light engine.

4. The method as recited in claim 3, wherein the light engine sequentially transitions through two or more colors and wherein the operating characteristic corresponds to a transition time between colors.

5. A pulse width modulation circuit, comprising:

a memory adapted to store a pixel value; and

a circuit configured to read the pixel value and to generate a pulse having a duration corresponding to the pixel value, the circuit being further configured to offset the pulse with respect to a start time and an end time of a refresh cycle of a spatial light modulator.

6. The pulse width modulation circuit as recited in claim 5, wherein the circuit generates the pulse centered with respect to the refresh cycle.

7. The pulse width modulation circuit as recited in claim 5, wherein the spatial light modulator is illuminated by a light engine and wherein an amount the pulse is offset is in accordance with an operating characteristic of the light engine.

8. The pulse width modulation circuit as recited in claim 7, wherein the light engine is adapted to sequentially transition through two or more colors and wherein the operating characteristic corresponds to a transition time between colors.

9. The pulse width modulation circuit as recited in claim 5, wherein the circuit comprises a delay circuit configured to provide the offset.

10. The pulse width modulation circuit as recited in claim 5, wherein the circuit comprises a part select circuit configured to divide the refresh cycle into at least a plurality of parts, the part select circuit being further configured to apportion the duration of the pulse between the plurality of parts of the refresh cycle.

11. The pulse width modulation circuit as recited in claim 5, wherein the circuit comprises a look-up-table having at least a first entry and a second entry corresponding to the pixel value, wherein the first entry corresponds to an inactive state for the pulse and the second entry corresponds to an active state for the pulse.

12. A system, comprising:

a spatial light modulator including at least one pixel;

a pixel source including pixel data corresponding to the pixel;

a memory circuit connected to the pixel source and configured to store a pixel value corresponding to the pixel data;

a pulse width modulation circuit connected between the memory circuit and the spatial light modulator, the pulse width modulation circuit adapted to generate a pulse to drive the pixel of the spatial light modulator, wherein a duration of the pulse corresponds to the pixel value and wherein the pulse is offset with respect to a start time and an end time of a refresh cycle of the spatial light modulator; and

a control circuit connected to at least one of the memory circuit, the spatial light modulator, and the pulse width modulation circuit.

13. The system as recited in claim 12, wherein the pulse width modulation circuit generates the pulse centered with respect to the refresh cycle.

14. The system as recited in claim 12, further comprising:

a light engine adapted to illuminate the spatial light modulator, wherein an amount the pulse is offset is in accordance with an operating characteristic of the light engine.

15. The system as recited in claim 14, wherein the light engine is adapted to sequentially transition through two or more colors and wherein the operating characteristic corresponds to a transition time between colors.

16. The system as recited in claim 12, wherein the pulse width modulation circuit comprises a delay circuit configured to provide the offset.

17. The system as recited in claim 12, wherein the pulse width modulation circuit comprises a part select circuit configured to divide the refresh cycle into a plurality of parts, the part select circuit being further configured to apportion the duration of the pulse between the plurality of parts of the refresh cycle.

18. The system as recited in claim 17, wherein the plurality of parts includes at least a first part and a second part of the refresh cycle and the pulse width modulation circuit comprises an up-down counter, and wherein the up-down counter is adapted to count up during the first part of the refresh cycle and down during the second part of the refresh cycle.

19. The system as recited in claim 18, wherein a state of the pixel is determined by comparing a value stored in the part select circuit with a value of the up-down counter.

20. The system as recited in claim 12, wherein the pulse width modulation circuit comprises a look-up-table having at least a first entry and a second entry corresponding to the pixel value, wherein the first entry corresponds to an inactive state for the pulse and the second entry corresponds to an active state for the pulse.