Method and apparatus for adaptive power consumption

• US 20040039954A1
• Filed: 08/22/2002
• Published: 02/26/2004
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Welzen, James L. van, White, Jonathan B.
• Granted Patent: US 7,634,668 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for adapting power consumption of a processor based upon an application demand is provided. The method initiates with determining an application demand based upon a current processing operation. Then, a time interval associated with the application demand is determined. Next, unnecessary power consuming functions for the application demand are determined. Then, a clock frequency for the unnecessary power consuming functions is reduced for the time interval. In one embodiment, the power is terminated to the unnecessary power consuming functions. In another embodiment, the clock frequency of the processor is adjusted for at least a portion of the time interval. A program interface for adapting power consumption of a computer system, processor instructions for adapting power consumption of a computer system and a processor are included.

Claims

1. A method for adapting power consumption of a processor based upon an application demand, comprising:

determining an application demand based upon a current processing operation;

determining a time interval associated with the application demand;

determining unnecessary power consuming functions for the application demand; and

reducing a clock frequency for the unnecessary power consuming functions for the time interval.

2. The method of claim 1, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

3. The method of claim 1, wherein the unnecessary power consuming functions include one of a 3-dimensional graphics pipeline and a 2-dimensional graphics pipeline, each pipeline associated with a graphics processing unit.

4. The method of claim 1, wherein the current processing operation is associated with playback of a movie on a portable computer.

5. A method for adapting power consumption of a processor based upon an application demand, comprising:

determining an application demand;

determining a time interval associated with the application demand;

determining unnecessary power consuming functions associated with the processor;

terminating power to the unnecessary power consuming functions; and

adjusting a clock frequency of the processor for at least a portion of the time interval.

6. The method of claim 5, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

7. The method of claim 5, wherein the unnecessary power consuming functions include one of a 3-dimensional graphics pipeline and a 2-dimensional graphics pipeline, each pipeline associated with a graphics processing unit.

8. The method of claim 5, wherein the current processing operation is associated with playback of a movie on a portable computer.

9. The method of claim 5, wherein the method operation of adjusting a clock frequency of the processor for at least a portion of the time interval includes, providing an interface in communication with the processor, the interface enabling instructions to be written to the processor to adjust the clock frequency.

10. A method of adapting processing power of a processor, comprising:

tracking a load level for a time interval;

monitoring idle time during the time interval;

determining a percentage of maximum processing power of the processor sufficient for the load level; and

adjusting the processing power of the processor to the determined percentage.

11. The method of claim 10, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

12. The method of claim 10, wherein the load level is associated with video decoding operations.

13. The method of claim 10, wherein the processing power of the processor is set to provide enough power to the processor to track time when the processor is idle.

14. The method of claim 10, wherein the method operation of adjusting the processing power of the processor to the determined percentage includes,

providing an interface in communication with the processor, the interface enabling instructions to be written to the processor to adjust the processing power.

15. A method of adapting processing power of a processor, comprising:

tracking a plurality of load levels, each of the load levels being associated with a time interval;

monitoring idle time during each time interval;

determining a percentage of maximum processing power of the processor sufficient for each load level; and

adjusting the processing power of the processor to the determined percentage for each load level.

16. The method as recited in claim 15, wherein at least some of the plurality of load levels correspond to an intra-frame (I-frame), a predicted-frame (P-frame) and a bi-directional-frame (B-frame) of a Moving Pictures Expert Group (MPEG) standard.

17. The method of claim 15, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

18. The method of claim 15, wherein each of the load levels is associated with video decoding operations.

19. The method of claim 15, wherein the processing power of the processor is set to provide enough power to the processor to track time when the processor is idle.

20. The method of claim 15, wherein the method operation of adjusting the processing power of the processor to the determined percentage for each load level includes,

providing an interface in communication with the processor, the interface enabling instructions to be written to the processor to adjust the processing power to the determined percentage for each load level.

21. A program interface for adapting power consumption of a computer system, comprising:

an interface for adjusting a clock frequency of a processor, the interface enabling the adjustment of the clock frequency in response to a determined processing load level, wherein the adjustment of the clock frequency is defined to vary as a function of time.

22. The interface of claim 21, wherein the interface is one of an application program interface and an operating system interface.

23. The interface of claim 21, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

24. The interface of claim 21, wherein the determined processing load level is associated with video decoding.

25. A program interface for adapting power consumption of a computer system, comprising:

an interface for adjusting a voltage of a processor, the interface enabling the adjustment of the voltage in response to a determined processing load level, wherein the adjustment of the voltage is defined to vary as a function of time.

26. The interface of claim 25, wherein the interface is one of an application program interface and an operating system interface.

27. The interface of claim 25, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

28. The interface of claim 25, wherein the determined processing load level is associated with video decoding.

29. Processor instructions for adapting power consumption of a computer system, comprising:

computer code configured to trigger an adjustment of a clock frequency of a processor, the computer code enabling the adjustment of the clock frequency in response to a determined processing load level, wherein the adjustment of the clock frequency is defined to vary as a function of time.

30. The processor instructions of claim 29, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

31. The processor instructions of claim 29, wherein the determined processing load level is associated with video decoding operations.

32. The processor instructions of claim 31, wherein the clock frequency is adjusted for each frame of a motion picture expert group (MPEG) standard.

33. The processor instructions as recited in claim 29, wherein the computer code causes a value to be stored in a control register.

34. Processor instructions for adapting power consumption of a computer system, comprising:

computer code configured to trigger an adjustment of a voltage of a processor, the computer code enabling the adjustment of the voltage in response to a determined processing load level, wherein the adjustment of the voltage is defined to vary as a function of time.

35. The processor instructions of claim 34, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

36. The processor instructions of claim 34, wherein the determined processing load level is associated with video decoding operations.

37. The processor instructions of claim 36, wherein the clock frequency is adjusted for each frame of a motion picture expert group (MPEG) standard.

38. The processor instructions as recited in claim 34, wherein the computer code causes a value to be stored in a control register.

39. A processor apparatus, comprising:

an instruction decoder configured to identify an instruction that writes a value to a control register, the control register affecting a clock frequency used to clock the processor apparatus.

40. The apparatus of claim 39, wherein the instruction is a privileged instruction.

41. The processor apparatus of claim 39, wherein the processor apparatus is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

42. The processor apparatus of claim 39 wherein the processor apparatus is a component of a portable computing device.

43. A processor apparatus, comprising:

an instruction decoder configured to identify an instruction that writes a value to a control register, the control register affecting a voltage source used to supply power to the processor apparatus.

44. The apparatus of claim 43, wherein the instruction is a privileged instruction.

45. The processor apparatus of claim 43, wherein the processor apparatus is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

46. The processor apparatus of claim 43 wherein the processor apparatus is a component of a portable computing device.