Method for effectively embedding various integrated circuits within field programmable gate arrays

• US 20040040005A1
• Filed: 01/17/2003
• Published: 02/26/2004
• Est. Priority Date: 01/17/2002
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Carison, Randolph C.
• Granted Patent: US 7,082,591 B2
• Time in Patent Office: Days
• US Class Current: 716/8
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A chip stack includes a field programmable gate array (FPGA) and an auxiliary component coupled to the FPGA with intercommunicated clock, control and/or data signals. The auxiliary component has a functionality mapped into the FPGA. The pin definition of the FPGA is redefined so that the FPGA and the auxiliary component in combination operate as a modified FPGA. A test circuit is programmed into the FPGA to exercise the auxiliary component to test functionality and timing performance at full speed. The functionality of the auxiliary component mapped into the FPGA is parameterized, such as for the data word width for reading and/or writing data words of different lengths into the auxiliary component in both an aligned and nonaligned manner. A memory interface allows multiple auxiliary circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.

Claims

1. An improvement in an apparatus comprising a plurality of pre-formed IC chips encapsulated in stackable layers in an electronic package, including at least one field programmable gate array (FPGA), the improvement comprising:

a field programmable gate array (FPGA); and

at least one auxiliary logic component coupled to the FPGA with at least one intercommunicated clock, control and/or data signal between the FPGA and the auxiliary logic component.

2. The improvement of claim 1 where the auxiliary logic component and the FPGA are interconnected through discrete interconnections with each other.

3. The improvement of claim 1 where the auxiliary logic component and the FPGA are interconnected through commonly shared connections.

4. The improvement of claim 1 further comprising a plurality of auxiliary logic components, and where the plurality of auxiliary logic components and the FPGA are interconnected through commonly shared connections.

5. The improvement of claim 1 further comprising a plurality of FPGAs, and where the plurality of FPGAs and the auxiliary logic component are interconnected through commonly shared connections.

6. The improvement of claim 1 further comprising a plurality of FPGAs, and a plurality of auxiliary logic components, and where the plurality of FPGAs and the plurality of auxiliary logic components are interconnected through commonly shared connections.

7. The improvement of claim 1 where the auxiliary component has a functionality and where the functionality of the auxiliary component is mapped into the FPGA.

8. The improvement of claim 7 where the FPGA has a pin definition and where the mapping of the functionality into the FPGA redefines the FPGA pin definition.

9. The improvement of claim 8 where the FPGA with redefined FPGA pin definition and the auxiliary logic component function in combination as a modified FPGA.

10. The improvement of claim 1 wherein a test circuit is programmed into the FPGA to exercise the auxiliary logic component.

11. The improvement of claim 1 where the auxiliary logic component is a memory circuit.

12. The improvement of claim 11 wherein a test circuit is programmed into the FPGA to exercise the memory circuit.

13. The improvement of claim 12 further comprising a plurality of memory circuits as auxiliary logic components and wherein the test circuit exercises each of the memory circuits to test functionality and timing performance.

14. The improvement of claim 10 wherein the test circuit exercises the auxiliary logic component to test functionality and timing performance.

15. The improvement of claim 14 wherein the test circuit tests functionality and timing performance at full speed of operation of the auxiliary logic component.

16. The improvement of claim 7 wherein the functionality of the auxiliary logic component mapped into the FPGA is parameterized.

17. The improvement of claim 16 wherein the parameterized functionality of the auxiliary logic component mapped into the FPGA comprises an arbitrary data word width.

18. The improvement of claim 17 wherein the parameterized functionality of the auxiliary component mapped into the FPGA comprises reading and/or writing data words of different lengths into the auxiliary component in both an aligned and a nonaligned manner.

19. The improvement of claim 16 wherein the parameterized functionality of the auxiliary logic component mapped into the FPGA comprises a memory interface that allows multiple auxiliary logic circuits to be accessed through the FPGA either together to generate a wider data word or serially to achieve a greater memory depth.

33. The improvement of claim 14 wherein the test circuit tests functionality and timing performance at full speed of operation of the auxiliary logic component.

20. An improvement in a method of operating a field programmable gate array (FPGA) included in a plurality of pre-formed IC chips encapsulated in stackable layers in an electronic package, the improvement comprising intercommunicating the field programmable gate array (FPGA) and at least one auxiliary logic component coupled to the FPGA through at least one common clock, control and/or data signal between the FPGA and the auxiliary logic component.

21. The improvement of claim 20 where intercommunicating the field programmable gate array (FPGA) and at least one auxiliary logic component comprises interconnecting the auxiliary logic component and the FPGA through discrete interconnections with each other.

22. The improvement of claim 20 where intercommunicating the field programmable gate array (FPGA) and at least one auxiliary logic component comprises interconnecting the auxiliary logic component and the FPGA through commonly shared connections.

23. The improvement of claim 20 further comprising a plurality of auxiliary logic components, and where intercommunicating the field programmable gate array (FPGA) and auxiliary logic component comprises interconnecting the plurality of auxiliary logic component and the FPGA through commonly shared connections.

24. The improvement of claim 20 further comprising a plurality of FPGAs, and where intercommunicating the plurality of field programmable gate arrays and the auxiliary logic component comprises interconnecting the plurality of FPGAs and the auxiliary logic components through commonly shared connections.

25. The improvement of claim 20 further comprising a plurality of FPGAs, and a plurality of auxiliary logic components, and where intercommunicating the plurality of field programmable gate arrays and the auxiliary logic component comprises interconnecting the plurality of FPGAs and the plurality of auxiliary logic components through commonly shared connections.

26. The improvement of claim 20 where the auxiliary component has a functionality and further comprising mapping the functionality of the auxiliary component into the FPGA.

27. The improvement of claim 26 where the FPGA has a pin definition and where mapping of the functionality into the FPGA comprises redefining the FPGA pin definition.

28. The improvement of claim 27 further comprising operating the FPGA with redefined FPGA pin definition and the auxiliary logic component in combination as a modified FPGA.

29. The improvement of claim 20 further comprising programming a test circuit into the FPGA and exercising the auxiliary logic component with the test circuit programmed into the FPGA.

30. The improvement of claim 29 wherein exercising the auxiliary logic component with the test circuit programmed into the FPGA comprises exercising a memory circuit.

31. The improvement of claim 30 further comprising exercising a plurality of memory circuits as auxiliary logic components to test functionality and timing performance.

32. The improvement of claim 29 wherein exercising the auxiliary logic component with the test circuit programmed into the FPGA tests functionality and timing performance of the auxiliary logic component.

34. The improvement of claim 26 wherein mapping the functionality of the auxiliary component into the FPGA comprises mapping a parameterized functionality of the auxiliary logic component mapped into the FPGA.

35. The improvement of claim 34 wherein mapping a parameterized functionality of the auxiliary logic component mapped into the FPGA comprises mapping reading and/or writing an arbitrary data word width into or out of the auxiliary logic component by means of the FPGA.

36. The improvement of claim 35 wherein mapping reading and/or writing an arbitrary data word width into or out of the auxiliary logic component by means of the FPGA comprises reading and/or writing data words of different lengths into the auxiliary component in both an aligned and a nonaligned manner.

37. The improvement of claim 34 wherein mapping a parameterized functionality of the auxiliary logic component mapped into the FPGA comprises accessing multiple auxiliary logic circuits through a memory interface coupled to the FPGA either to generate a wider data word or serially to achieve a greater memory depth.