CMOS image sensor apparatus with on-chip real-time pipelined JPEG compression module

• US 20040042668A1
• Filed: 08/27/2002
• Published: 03/04/2004
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Subbotin, Igor, Kaplinsky, Michael, Lin, Xiuhong
• Granted Patent: US 7,532,760 B2
• Time in Patent Office: Days
• US Class Current: 382/232
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A CMOS imager in which a CMOS image sensor, a color image processing module and an image compression module are all provided on a single die. Both the color image processing module and the image compression module incorporate pipelined architectures to process the image data at a video rate in a massively parallel fashion.

Claims

1. A CMOS imaging device integrated on a single chip, comprising:

a CMOS image sensor;

a color image processing module; and

an image compression module.

2. The CMOS imaging device of claim 1, wherein said image compression module has a pipelined architecture for processing image data in a parallel fashion at video rates without requiring a full frame memory buffer.

3. The CMOS imaging device of claim 2, wherein said image compression module implements JPEG compression at video rates.

4. The CMOS imaging device of claim 1, wherein said color imaging processing module converts digitized imager data from first format which is native to a CMOS imager to a second format suitable for image compression.

5. The CMOS imaging device of claim 4 wherein said first format is RGB and said second format is YCrCb.

6. The CMOS imaging device of claim 3, further comprising a plurality of line buffers at a front end of the compression module to allow two-dimensional processing.

7. The CMOS imaging device of claim 3, further comprising an SRAM addressing scheme to allow maximum utilization rate of memory, comprising reading and writing to one SRAM at the same rate without overwriting.

8. The CMOS imaging device of claim 7, wherein an address calculation formula is used in SRAM addressing.

9. The CMOS imaging device of claim 3, wherein said JPEG image compression module implements baseline JPEG and contains one or more of a DCT module, a Zig-Zag scan module, a quantization module and an entropy encoder module.

10. The CMOS imaging device of claim 3, further comprising a buffer at the output of the image compression module to allow for periods of fixed-rate data output interspersed with periods of inactivity.

11. The CMOS imager device of claim 10, wherein the output buffer is a dual-ported memory provided with a pointer control block, such that the buffer functions as a FIFO memory.

12. The CMOS imager device of claim 11, wherein the pointer control block allows for the storage of the output of the encoder as soon as it becomes available, while allowing independent retrieval of data based on external requests.

13. The CMOS imager device of claim 11, further comprising a FIFO &

Register &

CPU control block to enable register access and FIFO access via a single CPU memory bus.

14. The CMOS imager device of claim 11, wherein the FIFO &

Register &

CPU control block generates an INT signal reflecting the current state of the FIFO.

15. The CMOS imager device of claim 11, wherein the FIFO pointer control block generates half-full and almost-empty/full flags reflecting the state of the content of the FIFO memory.

16. The CMOS imager device of claim 11, wherein the FIFO outputs are connected directly to a data/memory bus of a system, allowing for access to the system to be performed over standard system communication channels.

17. The CMOS imager device of claim 16, wherein access to registers and control functions of the imager system is also performed over said data/memory bus.

18. The CMOS imager device of claim 13, wherein control signals are provided to distinguish between image access, register write, and register read traffic over the output pins.

19. The CMOS imager device of claim 1, further comprising circuitry for multiplexing compressed and uncompressed video to an input port of the FIFO memory.

20. A process for processing image data from a CMOS imager device, comprising the steps of:

converting an image to image data using a CMOS image sensor;

color image processing said image data from first format which is native to a CMOS imager to a second format more suitable for image compression; and

compressing the image data using a processing module having a pipelined architecture for processing image data in a parallel fashion at video rates without requiring a full frame memory buffer.

21. The process of claim 20, wherein said step of compressing the image comprises JPEG compression at video rates.

22. The process of claim 21, wherein an SRAM addressing scheme is used to allow maximum utilization rate of memory, said SRAM addressing scheme comprising reading and writing to one SRAM at the same rate without overwriting.

23. The process of claim 20, wherein said step of color image processing comprises converting digitized imager data from first format which is native to a CMOS imager to a second format more suitable for image compression.

24. The process of claim 20, wherein said first format is RGB and said second format is YCrCb.

25. A processing system, comprising:

a processor for receiving and processing image data; and

an image data generator for supplying image data to the processor, the image data generator comprising

a CMOS image sensor;

a color image processing module; and

an image compression module.