System and method for transferring data over a communication medium using double-buffering

• US 20040044811A1
• Filed: 08/30/2002
• Published: 03/04/2004
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Vrancic, Aljosa
• Granted Patent: US 6,985,977 B2
• Time in Patent Office: Days
• US Class Current: 710/53
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Claims

1. A method for transferring data in a system including a host computer system coupled through a communication medium to a data acquisition device, wherein the data acquisition device comprises a first read buffer and a second read buffer, the method comprising:

the data acquisition device reading first data from the host computer and storing the first data in the first read buffer;

transferring the first data out from the first read buffer;

the data acquisition device reading second data from the host computer and storing the second data in the second read buffer concurrently with said transferring the first data out from the first read buffer.

2. The method of claim 1, further comprising:

determining if there are more data to transfer;

if there are no more data to transfer, then terminating said transferring data.

3. The method of claim 1, further comprising:

transferring the second data out from the second read buffer after completion of said transferring the first data out from the first read buffer.

4. The method of claim 3, further comprising:

the data acquisition device reading third data from the host computer and storing the third data in the first read buffer concurrently with said transferring the second data out from the second read buffer.

5. The method of claim 4, further comprising:

after said data acquisition device reading third data from the host computer and storing the third data in the first read buffer concurrently with said transferring the second data out from the second read buffer, determining if there are more data to transfer;

if there are no more data to transfer, then terminating said transferring data.

6. The method of claim 4, wherein the data acquisition device includes a first direct memory access (DMA) channel and a second DMA channel;

wherein the first DMA channel performs said reading first data from the host computer and storing the first data in the first read buffer, reading second data from the host computer and storing the second data in the second read buffer, and reading third data from the host computer and storing the third data in the first read buffer; and

wherein the second DMA channel performs said transferring the first data out from the first read buffer and said transferring the second data out from the second read buffer.

7. The method of claim 4, wherein the data acquisition device reads data into one of the first read buffer and the second read buffer concurrently with transferring data out from the other one of the second read buffer and the first read buffer, respectively, in a double buffered fashion.

8. The method of claim 7,

wherein the data acquisition device includes a first direct memory access (DMA) channel and a second DMA channel;

wherein the first DMA channel reads data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer, respectively.

9. The method of claim 8, the method further comprising:

synchronizing the first DMA channel and the second DMA channel after said first DMA channel reads data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer.

10. The method of claim 9, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing a pause command, thereby pausing itself;

the second DMA channel entering the synchronization point; and

the second DMA channel issuing a continue command, thereby awakening the first DMA channel;

wherein, after said second DMA channel issuing the continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

11. The method of claim 9, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing a continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

the first DMA channel issuing a pause command, thereby pausing itself;

the second DMA channel entering the synchronization point; and

the second DMA channel issuing a continue command, thereby awakening the first DMA channel;

the second DMA channel issuing a pause command, thereby pausing itself;

the first DMA channel issuing a continue command, thereby awakening the second DMA channel;

wherein, after said first DMA channel issuing the continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

12. The method of claim 9, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing a single atomic command, comprising;

issuing a pause command; and

issuing a continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

wherein the first DMA channel does not check its state and pause itself if requested until said issued single atomic command is executed;

the second DMA channel entering the synchronization point;

the second DMA channel issuing a single atomic command, comprising;

issuing a pause command; and

issuing a continue command, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein the second DMA channel does not check its state and pause itself if requested until said issued single atomic command is executed;

the first DMA channel issuing a second continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

the second DMA channel issuing a second continue command, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, after said first DMA channel issuing the second continue command, and the second DMA channel issuing a second continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

13. The method of claim 9, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing single atomic command, comprising;

issuing a continue command, thereby awakening the second DMA channel if the second DMA channel is paused; and

issuing a pause command, thereby pausing itself;

wherein, during said issuing the single atomic execution command, the second DMA channel is excluded from issuing other atomic commands;

the second DMA channel entering the synchronization point;

the second DMA channel issuing single atomic command, comprising;

issuing a continue command, thereby awakening the first DMA channel if the first DMA channel is paused; and

issuing a pause command, thereby pausing itself;

wherein, during said issuing the single atomic execution command, the first DMA channel is excluded from issuing other atomic commands;

the first DMA channel issuing a second continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

the second DMA channel issuing a second continue command, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, after said first DMA channel issuing the second continue command, and the second DMA channel issuing a second continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

14. The method of claim 4,

wherein the data acquisition device reading first data comprises the data acquisition device reading first requested data and first pre-fetch data;

wherein the data acquisition device reading second data comprises the data acquisition device reading second requested data and second pre-fetch data;

wherein the data acquisition device reading third data comprises the data acquisition device reading third requested data and third pre-fetch data.

15. The method of claim 14, further comprising:

transferring the first requested data from the first read buffer to a first temporary memory after reading the first data into the first read buffer, wherein said transferring the first requested data from the first read buffer to the first temporary memory location operates to satisfy a first read request;

transferring the second requested data from the second read buffer to a second temporary memory location after reading the second data into the second read buffer, wherein said transferring the second requested data from the second read buffer to the second temporary memory location operates to satisfy a second read request, and

transferring the third requested data from the first read buffer to the first temporary memory location after reading the third data into the first read buffer, wherein said transferring the third requested data from the first read buffer to the first temporary memory location operates to satisfy a third read request.

16. The method of claim 3,

wherein said transferring the first data out from the first read buffer comprises transferring the first data from the first read buffer to a FIFO memory;

and

wherein said transferring the second data out from the second read buffer comprises transferring the second data from the second read buffer to a FIFO memory.

17. The method of claim 1, wherein said transferring the first data out from the first read buffer is performed after said reading the first data from the host computer and storing the first data in the first read buffer.

18. A method for transferring data in a system including a host computer system coupled through a communication medium to a data acquisition device, wherein the data acquisition device comprises a first read buffer and a second read buffer, wherein the first read buffer stores first data, the method comprising:

transferring the first data out from the first read buffer;

the data acquisition device reading second data from the host computer and storing the second data in the second read buffer concurrently with said transferring the first data out from the first read buffer;

transferring the second data out from the second read buffer after completion of said transferring the first data out from the first read buffer; and

the data acquisition device reading third data from the host computer and storing the third data in the first read buffer concurrently with said transferring the second data out from the first second buffer.

19. The method of claim 18, further comprising:

after said data acquisition device reading second data from the host computer and storing the second data in the second read buffer concurrently with said transferring the first data out from the first read buffer, determining if there are more data to transfer; and

if there are no more data to transfer, then terminating said transferring data.

20. The method of claim 19,

wherein the data acquisition device includes a first direct memory access (DMA) channel and a second DMA channel;

wherein the first DMA channel performs said reading second data from the host computer and storing the second data in the second read buffer, and reading third data from the host computer and storing the third data in the first read buffer; and

wherein the second DMA channel performs said transferring the first data out from the first read buffer and said transferring the second data out from the second read buffer.

21. The method of claim 18,

wherein the data acquisition device reads data into one of the first read buffer and the second read buffer concurrently with transferring data out from the other one of the second read buffer and the first read buffer, respectively, in a double buffered fashion.

22. The method of claim 21,

wherein the data acquisition device includes a first direct memory access (DMA) channel and a second DMA channel;

and

wherein the first DMA channel reads data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer, respectively.

23. The method of claim 22, the method further comprising:

synchronizing the first DMA channel and the second DMA channel after said first DMA channel reads data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer.

24. The method of claim 23, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing a pause command, thereby pausing itself;

the second DMA channel entering the synchronization point; and

the second DMA channel issuing a continue command, thereby awakening the first DMA channel;

wherein, after said second DMA channel issuing the continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

25. The method of claim 23, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing a continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

the first DMA channel issuing a pause command, thereby pausing itself;

the second DMA channel entering the synchronization point; and

the second DMA channel issuing a continue command, thereby awakening the first DMA channel;

the second DMA channel issuing a pause command, thereby pausing itself;

the first DMA channel issuing a continue command, thereby awakening the second DMA channel;

wherein, after said first DMA channel issuing the continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

26. The method of claim 23, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing single atomic command, comprising;

issuing a pause command; and

issuing a continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

wherein, the first DMA channel does not check its state and pause itself if requested until said issued the single atomic command is executed;

the second DMA channel entering the synchronization point;

the second DMA channel issuing single atomic command, comprising;

issuing a pause command; and

issuing a continue command, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, the second DMA channel does not check its state and pause itself if requested until said issued the single atomic command is executed;

the first DMA channel issuing a second continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

the second DMA channel issuing a second continue command, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, after said first DMA channel issuing the second continue command, and the second DMA channel issuing a second continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

27. The method of claim 23, wherein said synchronizing comprises:

the first DMA channel entering a synchronization point;

the first DMA channel issuing single atomic command, comprising;

issuing a continue command, thereby awakening the second DMA channel if the second DMA channel is paused; and

issuing a pause command, thereby pausing itself;

wherein, during said issuing the single atomic execution command, the second DMA channel is excluded from issuing other atomic commands;

the second DMA channel entering the synchronization point;

the second DMA channel issuing single atomic command, comprising;

issuing a continue command, thereby awakening the first DMA channel if the first DMA channel is paused; and

issuing a pause command, thereby pausing itself;

wherein, during said issuing the single atomic execution command, the first DMA channel is excluded from issuing other atomic commands;

the first DMA channel issuing a second continue command, thereby awakening the second DMA channel if the second DMA channel is paused;

the second DMA channel issuing a second continue command, thereby awakening the first DMA channel if the first DMA channel is paused;

wherein, after said first DMA channel issuing the second continue command, and the second DMA channel issuing a second continue command, the first DMA channel and the second DMA channel are operable to proceed with said transferring data in a synchronous manner.

28. A system for transferring data over a communication medium, the system comprising:

a communication medium;

a data acquisition device coupled to a first end of the communication medium, wherein the data acquisition device comprises a first read buffer and a second read buffer; and

a host computer system coupled to a second end of the communication medium, wherein the host computer system is operable to communicate through the communication medium to the data acquisition device;

wherein the data acquisition device is operable to;

read first data from the host computer and store the first data in the first read buffer;

transfer the first data out from the first read buffer; and

read second data from the host computer and store the second data in the second read buffer concurrently with the transfer of the first data out from the first read buffer.

29. The system of claim 28, wherein the data acquisition device is further operable to:

determine if there are more data to transfer; and

if there are no more data to transfer, terminate said transferring data.

30. The system of claim 28, wherein the data acquisition device is further operable to transfer the second data out from the second read buffer after completion of said transfer of the first data out from the first read buffer.

31. The system of claim 30, wherein the data acquisition device is further operable to read third data from the host computer and store the third data in the first read buffer concurrently with said transfer of the second data out from the second read buffer.

32. The system of claim 31, wherein the data acquisition device is further operable to:

after said data acquisition device reading third data from the host computer and storing the third data in the first read buffer concurrently with said transferring the second data out from the second read buffer, determine if there are more data to transfer; and

if there are no more data to transfer, terminate said transferring data.

33. The system of claim 31,

wherein the first data comprise first requested data and first pre-fetch data;

wherein the second data comprise second requested data and second pre-fetch data; and

wherein the third data comprise third requested data and third pre-fetch data.

34. The system of claim 33,

wherein the data acquisition device being operable to transfer the first data out from the first read buffer comprises the data acquisition device being operable to transfer the first requested data from the first read buffer to a first temporary memory, wherein said transferring the first requested data from the first read buffer to the first temporary memory location operates to satisfy a first read request;

and

wherein the data acquisition device being operable to transfer the second data out from the second read buffer comprises the data acquisition device being operable to transfer the second data from the second read buffer to a second temporary memory location, wherein said transferring the second requested data from the second read buffer to the second temporary memory location operates to satisfy a second read request.

35. The system of claim 28,

wherein the data acquisition device comprises a first direct memory access (DMA) channel and a second DMA channel;

and

wherein the first DMA channel reads data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer, respectively.

36. The system of claim 35, wherein, after said first DMA channel is operable to read data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer, respectively, the data acquisition device is further operable to:

determine if there are more data to transfer; and

if there are no more data to transfer, terminate said transferring data.

37. The system of claim 35, wherein, after said first DMA channel reads data into one of the first read buffer and the second read buffer concurrently with the second DMA channel transferring data out from the other one of the second read buffer and the first read buffer, the data acquisition device is further operable to:

synchronize the first DMA channel and the second DMA channel.

38. A method for transferring data in a system including a host computer system coupled through a communication medium to a data acquisition device, the method comprising:

configuring a data acquisition device for a data input/output (I/O) operation, wherein the data acquisition device comprises a first read buffer, a second read buffer, a FIFO buffer, a first direct memory access (DMA) channel and a second DMA channel;

the data acquisition device issuing a first read request for first data from the host computer;

reading second data from the host computer into the first read buffer in response to the data acquisition device issuing the first read request for the first data, wherein the second data includes the first data;

the first DMA channel programming the second DMA channel to read data from the first read buffer into the FIFO buffer;

the second DMA channel reading data from the first read buffer into the FIFO buffer after said programming;

while the second DMA channel is reading data from the first read buffer into the FIFO buffer,

the data acquisition device issuing a second read request for third data from the host computer;

reading fourth data from the host computer into the second read buffer in response to the data acquisition device issuing the second read request for the third data, wherein the fourth data includes the third data;

the first DMA channel programming the second DMA channel to read data from the second read buffer into the FIFO buffer;

when the second DMA channel has completed reading the data from the first read buffer into the FIFO buffer,

the second DMA channel reading data from the second read buffer into the FIFO buffer;

the data acquisition device issuing a third read request for fifth data from the host computer;

the first DMA channel reading sixth data from the host computer into the first read buffer in response to the data acquisition device issuing the third read request for the fifth data, wherein the sixth data includes the fifth data.

39. The method of claim 38,

wherein the data acquisition device reading first data comprises the data acquisition device reading first requested data and first pre-fetch data;

wherein the data acquisition device reading second data comprises the data acquisition device reading second requested data and second pre-fetch data;

wherein the data acquisition device reading third data comprises the data acquisition device reading third requested data and third pre-fetch data.

40. The method of claim 38,

transferring the first requested data from the first read buffer to a first temporary memory after reading the first data into the first read buffer, wherein said transferring the first requested data from the first read buffer to the first temporary memory location operates to satisfy the first read request;

transferring the second data from the second read buffer to a second temporary memory location after reading the second data into the second read buffer, wherein said transferring the second requested data from the second read buffer to the second temporary memory location operates to satisfy the second read request, and

transferring the third data from the first read buffer to the first temporary memory location after reading the third data into the first read buffer, wherein said transferring the third requested data from the first read buffer to the first temporary memory location operates to satisfy the third read request.