Semiconductor device and method for fabricating the same

• US 20040046190A1
• Filed: 09/09/2003
• Published: 03/11/2004
• Est. Priority Date: 12/25/1998
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Inagawa, Hiroshi, Machida, Nobuo, Ooishi, Kentaro
• Granted Patent: US 6,861,703 B2
• Time in Patent Office: Days
• US Class Current: 257/268
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Claims

1. A metal insulator semiconductor field effect type semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces which are opposite to each other;

a trench formed in said semiconductor substrate to give a predetermined depth from the first main surface, said trench separating said first main surface of said semiconductor substrate into semiconductor island regions for forming metal insulator semiconductor field effect type cells, respectively;

a source region, a channel forming region and a drain region formed in the order of mention in the depth direction of the semiconductor island region from said first main surface of each said semiconductor island region;

a gate insulating film formed over the inside surface of said trench; and

a gate electrode formed over said gate insulating film so as to embed said trench with said gate electrode, said gate electrode extending vertically from said trench toward a position higher than said first main surface of said semiconductor island region.

2. A metal insulator semiconductor field effect type semiconductor device, comprising:

a semiconductor substrate having first and second main surfaces which are opposite to each other;

a trench formed in said semiconductor substrate to give a predetermined depth from the first main surface, said trench separating said first main surface of said semiconductor substrate into semiconductor island regions for forming metal insulator semiconductor field effect type cells, respectively;

a source region, a channel forming region and a drain region formed in the order of mention in the depth direction of said semiconductor island region from said first main surface of each said semiconductor island region;

a gate insulating film formed over the inside surface of said trench; and

a gate electrode formed over said gate insulating film so as to embed said trench with said gate electrode, said gate electrode having a protrusion extending vertically from said trench toward a position higher than said first main surface of said semiconductor island region.

3. A metal insulator semiconductor field effect type semiconductor device according to claim 2, further comprising:

a peripheral semiconductor region having the same conductivity type as that of said channel forming region formed in another portion of said first main surface of said semiconductor substrate; and

a conductive layer formed over said peripheral semiconductor region via an insulating film and electrically connected with said gate electrode.

4. A method of fabricating a trench-gate type semiconductor device, comprising the steps of:

making a trench in the main surface of a semiconductor substrate;

forming a gate insulating film on the inside surface of said trench;

forming a gate electrode to embed therewith said trench;

forming an insulating film over the main surface of said semiconductor substrate so that the film thickness on said gate electrode becomes greater than that on the main surface of said semiconductor substrate;

etching said insulating film to expose the main surface of said semiconductor substrate while leaving said thickly-formed insulating film on said gate electrode; and

selectively etching said semiconductor substrate relative to said insulating film so as to form the upper surface of said gate electrode, covered with said the insulating film, higher than the main surface of said semiconductor substrate.

9. A method according to any one of claims 4 to 8, wherein the impurity concentration of said gate electrode is set higher than that in the main surface of said semiconductor substrate.

5. A method of fabricating a trench-gate type semiconductor device, comprising the steps of:

making a trench in the main surface of a semiconductor substrate;

forming a gate insulating film on the inside surface of said trench;

forming a gate electrode to embed therewith said trench;

forming an insulating film over the main surface of said semiconductor substrate so that the film thickness on said gate electrode becomes greater than that on the main surface of said semiconductor substrate;

etching said insulating film to expose the main surface of said semiconductor substrate while leaving said thickly-formed insulating film on said gate electrode;

selectively etching said semiconductor substrate relative to said insulating film to form the upper surface of said gate electrode, covered with said insulating film, higher than the main surface of said semiconductor substrate; and

introducing, after selective etching, respective impurities from the main surface of said semiconductor substrate to form a channel forming region and a source region.

6. A method of fabricating a trench-gate type semiconductor device, comprising the steps of:

making a trench in the main surface of a semiconductor substrate;

forming a gate insulating film on the inside surface of said trench;

forming a polycrystalline silicon film to cover all over the main surface of said semiconductor substrate and embed therewith said trench;

oxidizing and etching said polycrystalline silicon film to form, in said trench, a gate electrode protruded from the main surface of said semiconductor substrate;

forming an insulating film over the main surface of said semiconductor substrate so that the film thickness on the gate electrode becomes greater than that on the main surface of said semiconductor substrate;

etching said insulating film to expose the main surface of said semiconductor substrate while leaving said thickly-formed insulating film on said gate electrode;

selectively etching said semiconductor substrate relative to said insulating film to form the upper surface of said gate electrode, covered with said insulating film, higher than the main surface of said semiconductor substrate; and

introducing, after selective etching, respective impurities from the main surface of said semiconductor substrate to form a channel forming region and a source region.

7. A method of fabricating a trench-gate type semiconductor device, comprising the steps of:

forming a field relaxing region of a first conductivity type in the peripheral portion of the main surface of a semiconductor substrate wherein a trench gate is to be formed;

forming, in the main surface of said semiconductor substrate, a trench wherein the trench gate is to be formed;

forming a gate insulating film in said trench;

forming a gate electrode in said trench;

forming an insulating film over the main surface of said semiconductor substrate so that the film thickness on said gate electrode becomes greater than that on the main surface of said semiconductor substrate;

removing said insulating film by etching to expose the main surface of said semiconductor substrate while leaving said thickly-formed insulating film on said gate electrode;

selectively removing said semiconductor substrate relative to said insulating film by etching to form the upper surface of said gate electrode, covered with the insulating film, higher than the main surface of said semiconductor substrate; and

introducing, after selective etching, respective impurities from the main surface of said semiconductor substrate to form a channel forming region of a first conductivity type and a source region of a second conductivity type.

8. A method of fabricating a trench-gate type semiconductor device, comprising the steps of:

making a trench in the main surface of a semiconductor substrate;

forming a gate insulating film in said trench;

forming a gate electrode in said trench;

forming an insulating film over the main surface of said semiconductor substrate so that the film thickness on said gate electrode becomes greater than that on the main surface of said semiconductor substrate;

forming a mask film over said insulating film on said gate electrode;

removing said insulating film by isotropic etching by using said mask film to expose the main surface of said semiconductor substrate while leaving said thickly-formed insulating film on said gate electrode; and

selectively removing said semiconductor substrate relative to said insulating film by etching to form the upper surface of said gate electrode, covered with the insulating film, higher than the main surface of said semiconductor substrate.

10. A fabricating method of a trench-gate type semiconductor device, comprising the steps of:

(1) forming, over the main surface of a semiconductor body containing impurities of a first conductivity type, a semiconductor layer containing impurities of the first conductivity type;

(2) forming a field insulating film in a selected region of the main surface of said semiconductor layer;

(3) making a trench in said semiconductor layer;

(4) forming a gate insulating film on the inside surface of said trench;

(5) embedding a gate conductive layer in said trench having said gate insulating film formed therein;

(6) etching the main surface of said semiconductor layer so that the main surface of said semiconductor layer becomes lower than the end portion of said gate conductive layer contiguous to said gate insulating film;

(7) introducing impurities of a second conductivity type in said semiconductor layer to form therein a first semiconductor region which is shallower than the bottom portion of said trench and is contiguous to said gate insulating film; and

(8) introducing impurities of the first conductivity type in said first semiconductor region to form therein a second semiconductor region which is shallower than said first semiconductor region and is contiguous to said gate insulating film.

11. A fabricating method according to claim 10, further comprising, prior to the step (7), forming, over said field insulating film, a polycrystalline silicon layer wherein a protective diode is to be formed.

12. A fabricating method according to claim 11, further comprising forming a back-to-back diode in said polycrystalline silicon layer.

13. A fabricating method according to claim 10, wherein said step (5) comprises:

forming a polycrystalline silicon layer on the main surface of said semiconductor layer including said trench;

etching back said polycrystalline silicon layer to leave said polycrystalline silicon layer inside said trench; and

oxidizing the main surface of said polycrystalline silicon layer in said trench.

14. A fabricating method of a semiconductor integrated circuit device, comprising the steps of:

etching an insulating film formed over the main surface of a semiconductor substrate and said semiconductor substrate to form a connecting hole reaching the inside of said semiconductor substrate;

selectively causing said insulating film to retreat relative to said semiconductor substrate and expanding said connecting hole to expose the main surface of said semiconductor substrate; and

forming a conductive film in said connecting hole.

15. A fabricating method according to claim 14, further comprising, prior to said step for expanding said connecting hole, introducing impurities through said connecting hole to form a high-concentration region in said semiconductor substrate.

16. A fabricating method according to claim 15, wherein said semiconductor substrate has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type formed therebelow,

said connecting hole extends to said second semiconductor region, and

said conductive film is electrically connected with said first semiconductor region, in said connecting hole, at the main surface and wall surface of said semiconductor substrate.

17. A fabricating method according to claim 16, further comprising, prior to said step for expanding said connecting hole, introducing impurities through said connecting hole to form, in said second semiconductor region, a third semiconductor region of the second conductivity type having an impurity concentration higher than that of said second semiconductor region.