Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
First Claim
1. In a phase locked loop system, a digitally-synthesized loop filter circuit comprising:
- a first circuit for providing a digital representation of a phase error signal of the phase locked loop;
a second circuit responsive to the digital phase error signal, for generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
a third circuit for generating an output signal corresponding to the accumulated digital phase error signal, said output signal useful for controlling an oscillator within the phase locked loop.
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Abstract
In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area. The power dissipation of the digital integration block is reduced by incorporating a decimation stage to reduce the required operating frequency of the remainder of the digital integration block.
59 Citations
28 Claims
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1. In a phase locked loop system, a digitally-synthesized loop filter circuit comprising:
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a first circuit for providing a digital representation of a phase error signal of the phase locked loop;
a second circuit responsive to the digital phase error signal, for generating a multi-bit accumulated digital phase error signal representing an accumulated value of successive values of the digital phase error signal; and
a third circuit for generating an output signal corresponding to the accumulated digital phase error signal, said output signal useful for controlling an oscillator within the phase locked loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification