Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

• US 20040053429A1
• Filed: 10/15/2003
• Published: 03/18/2004
• Est. Priority Date: 12/01/2000
• Status: Active Grant

• Current Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Muranaka, Masaya
• Granted Patent: US 6,941,536 B2
• Time in Patent Office: Days
• US Class Current: 438/17
• CPC Class Codes: G05B 19/128 the workpiece itself serves as a record carrier, e.g. by its form, by marks or codes on it
• CPC Class Codes: G05B 2219/31307 Identification structure is partly a copy of operating structure
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/4917 Crossed wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
• CPC Class Codes: Y02P 90/80 : Management or planning

Abstract

In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Claims

1. A method for identifying a semiconductor integrated circuit device, characterized by:

providing a semiconductor integrated circuit device with a plurality of identification elements formed to have the same form as one another through the same manufacturing process as one another; and

forming information which reflects a relation of magnitude in a physical amount of said plurality of identification elements to one another, said information being generated corresponding to variations in the physical amount of said plurality of identification elements, and setting the information reflecting the relation of magnitude as unique identification information of the semiconductor integrated circuit device.

2. A method for identifying a semiconductor integrated circuit device according to claim 1, characterized in that:

said plurality of identification elements are set within said semiconductor integrated circuit device.

3. A method for identifying a semiconductor integrated circuit device according to claim 2, characterized in that:

said unique identification information includes first identification information having a value which is set in said manufacturing process.

4. A method for identifying a semiconductor integrated circuit device according to claim 2, characterized in that:

said unique identification information comprises ordering information indicative of the order of magnitude of the physical amount of said plurality of identification elements.

5. A method for identifying a semiconductor integrated circuit device according to claim 3, characterized in that:

said plurality of identification elements each comprise a logic circuit, and said relation of magnitude in the physical amount is a relation of magnitude in an electric parameter of a plurality of logic circuits.

6. A method for identifying a semiconductor integrated circuit device according to claim 4, characterized in that:

said plurality of logic circuits output output voltages equal to respective threshold value voltages at their respective outputs as said electric parameter by their respective inputs being electrically connected to their respective outputs.

7. A method for identifying a semiconductor integrated circuit device according to claim 6, characterized in that:

said plurality of logic circuits comprise inverter circuits.

8. A method for identifying a semiconductor integrated circuit device according to claim 7, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET.

9. A method for identifying a semiconductor integrated circuit device according to claim 5, characterized in that:

said plurality of logic circuits comprise inverter circuits.

10. A method for identifying a semiconductor integrated circuit device according to claim 9, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET.

11. A method for identifying a semiconductor integrated circuit device according to claim 5, characterized in that:

said logic circuit is applied with a limited operating voltage when no operation is performed for determining the relation of magnitude in the electric parameter as said physical amount.

12. A method for identifying a semiconductor integrated circuit device according to claim 1, characterized in that:

said unique identification information comprises ordering information indicative of the order of magnitude of the physical amounts of said plurality of identification elements.

13. A method for identifying a semiconductor integrated circuit device according to claim 12, characterized in that:

said plurality of identification elements each comprise a logic circuit, and said relation of magnitude in the physical amount is a relation of magnitude in an electric parameter of a plurality of logic circuits.

14. A method for identifying a semiconductor integrated circuit device according to claim 13, characterized in that:

said logic circuit is applied with a limited operating voltage when no operation is performed for determining the relation of magnitude in the electric parameter as said physical amount.

15. A method for identifying a semiconductor integrated circuit device according to claim 13, characterized in that:

said plurality of logic circuits output output voltages equal to respective threshold value voltages at their respective outputs as said electric parameter by their respective inputs being electrically connected to their respective outputs.

16. A method for identifying a semiconductor integrated circuit device according to claim 15, characterized in that:

said plurality of logic circuits comprise inverter circuits.

17. A method for identifying a semiconductor integrated circuit device according to claim 16, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET.

18. A method for identifying a semiconductor integrated circuit device according to claim 13, characterized in that:

said plurality of logic circuits comprise inverter circuits.

19. A method for identifying a semiconductor integrated circuit device according to claim 18, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET.

20. A method for identifying a semiconductor integrated circuit device according to claim 1, characterized in that:

said plurality of identification elements each comprise a logic circuit, and said relation of magnitude in the physical amount is a relation of magnitude in an electric parameter of a plurality of logic circuits.

21. A method for identifying a semiconductor integrated circuit device according to claim 20, characterized in that:

said logic circuit is applied with a limited operating voltage when no operation is performed for determining the relation of magnitude in the electric parameter as said physical amount.

22. A method for identifying a semiconductor integrated circuit device according to claim 20, characterized in that:

said plurality of logic circuits output output voltages equal to respective threshold value voltages at their respective outputs as said electric parameter by their respective inputs being electrically connected to their respective outputs.

23. A method for identifying a semiconductor integrated circuit device according to claim 22, characterized in that:

said plurality of logic circuits comprise inverter circuits.

24. A method for identifying a semiconductor integrated circuit device according to claim 23, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET.

25. A method for identifying a semiconductor integrated circuit device according to claim 20, characterized in that:

said plurality of logic circuits comprise inverter circuits.

26. A method for identifying a semiconductor integrated circuit device according to claim 25, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET.

27. A method for manufacturing a semiconductor integrated circuit device for enabling reference to manufacturing information unique to the semiconductor integrated circuit device through a measurement of the semiconductor integrated circuit device, characterized in that:

said semiconductor integrated circuit device comprises a plurality of identification elements formed to have the same form as one another through the same manufacturing process as one another;

said semiconductor integrated circuit device is measured at one timing during a process of manufacturing said semiconductor integrated circuit device to form first information which reflects a relation of magnitude in a physical amount of said plurality of identification elements to one another, said information being generated corresponding to variations in the physical amount of said plurality of identification elements; and

said first information and second information including management information set in the manufacturing of said semiconductor integrated circuit device, which generates said first information, are held in an information holding device external to said semiconductor integrated circuit device as information unique to said semiconductor integrated circuit device,

whereby from third information which is the same type of information as said first information, generated through a measurement of said semiconductor integrated circuit device at a timing different from said one timing, said first information corresponded to said third information within said information holding device is referenced from said third information, and said second information can be referenced from said first information which is referenced based on said third information.

28. A method for manufacturing a semiconductor integrated circuit device, characterized by comprising the steps of:

forming a semiconductor integrated circuit device comprising a first chip, said semiconductor integrated circuit device having a plurality of identification elements formed to have the same form as one another and formed through the same manufacturing process as one another;

retrieving unique identification information from said plurality of identification elements in said semiconductor integrated circuit device comprising said first chip;

writing a plurality of unique identification information from said semiconductor integrated circuit device comprising said first chip, and operation modification information for said semiconductor integrated circuit device which provides the respective unique identification information, into a second chip; and

integrally assembling said first chip and second chip,

wherein said assembled second chip is configured to output said operation modification information to said first chip based on the unique identification information retrieved from said first chip integrally assembled therewith.

29. A method for manufacturing a semiconductor integrated circuit device according to claim 28, characterized in that:

said semiconductor integrated circuit device forms information including information which reflects a relation of magnitude in a physical amount of said plurality of identification elements to one another, said information being generated corresponding to variations in the physical amount of said plurality of identification elements, as said unique identification information.

30. A method for manufacturing a semiconductor integrated circuit device according to claim 29, characterized in that:

said information reflecting a relation of magnitude in a physical amount of said plurality of identification elements is based on comparison information which compares a physical amount of each identification element with physical amounts of a plurality of identification elements.

31. A method for manufacturing a semiconductor integrated circuit device according to claim 29, characterized in that:

said information reflecting a relation of magnitude in a physical amount of said plurality of identification elements is ordering information corresponded to the order of magnitude of the physical amounts of said plurality of identification elements.

32. A method for manufacturing a semiconductor integrated circuit device according to claim 28, characterized in that:

said first chip is a memory having a redundant circuit; and

said second chip stores a defective address of said first chip as said operation modification information.

33. A method for manufacturing a semiconductor integrated circuit device according to claim 28, characterized by further comprising the steps of:

conducting a test after sid first chip and second chip are assembled;

removing said second chip when a fault occurs in said test conducted in the assembled state, and collecting said semiconductor integrated circuit device comprising said first chip into a plurality of other semiconductor integrated circuit devices.

34. A method for manufacturing a semiconductor integrated circuit device according to claim 33, characterized in that:

said first chip and second chip are integrally encapsulated after screening in the assembled state.

35. A method for manufacturing a semiconductor integrated circuit device according to claim 34, characterized in that:

said first chip and second chip are assembled on a common mounting substrate.

36. A semiconductor integrated circuit device having a plurality of identification elements formed as the same form through the same manufacturing process as one another, and

configured to have unique identification information determined by said plurality of identification information, said semiconductor integrated circuit device characterized in that:

said unique identification information takes a state corresponded to a relation of magnitude in a physical amount of said plurality of identification elements to one another, caused by variations in characteristics of said plurality of identification elements.

37. A semiconductor integrated circuit device according to claim 36, characterized in that:

said unique identification information comprises a plurality of comparison information which compare the physical amount of each of said identification elements with those of said plurality of identification elements.

38. A semiconductor integrated circuit device according to claim 37, characterized in that:

said unique identification information comprises a plurality of comparison information corresponded to each of said plurality of identification elements; and

each of said plurality of comparison information comprises information comprised of a plurality of bits which compare the magnitudes of the mutual physical amounts of respective particular identification elements corresponded thereto and a plurality of a plurality of identification elements compared thereto.

39. A semiconductor integrated circuit device according to claim 38, characterized in that:

each of said plurality of comparison information is generated by data-converting information generated from a direct comparison of the physical amount of said particular identification element with physical amounts of a plurality of identification elements compared thereto.

40. A semiconductor integrated circuit device according to claim 38, characterized in that:

each of said plurality of comparison information comprises information having a compressed number of bits.

41. A semiconductor integrated circuit device according to claim 40, characterized in that:

said ordering information is comprised of a smaller number of bits than the number of comparisons of said particular identification element with a plurality of identification elements corresponded thereto.

42. A semiconductor integrated circuit device according to claim 37, characterized in that:

said ordering information comprises a plurality of ordering information corresponded to said plurality of identification elements, respectively

43. A semiconductor integrated circuit device according to claim 36, characterized in that:

said unique identification information comprises ordering information which reflects the order of magnitude of the physical amounts of said plurality of identification elements.

44. A semiconductor integrated circuit device according to claim 43, characterized in that:

said ordering information comprises a number of bits less than the number of comparisons of said particular identification element with a plurality of identification elements corresponded thereto.

45. A semiconductor integrated circuit device according to claim 36, characterized in that:

said unique identification information further includes first identification information having a value which is set in said manufacturing process.

46. A semiconductor integrated circuit device according to claim 36, characterized in that:

said identification elements each comprise a logic circuit, and said relationship of magnitude in the physical amount indicates a relation of magnitude in an electric parameter of the plurality of logic circuits.

47. A semiconductor integrated circuit device according to claim 46, characterized in that:

said plurality of logic circuits comprise inverter circuits.

48. A semiconductor integrated circuit device according to claim 46, characterized in that:

said plurality of logic circuits output output voltages equal to respective threshold value voltages at their respective outputs as said electric parameter by their respective inputs being electrically connected to their respective outputs.

49. A semiconductor integrated circuit device according to claim 48, characterized in that:

said plurality of logic circuits comprise inverter circuits.

50. A semiconductor integrated circuit device according to claim 49, characterized in that:

said identification element comprises a CMOS inverter circuit comprised of an N-channel MOSFET and a P-channel MOSFET, each of which is applied with an input voltage at an input to form an output voltage in accordance with variations at an output terminal thereof.

51. A semiconductor integrated circuit device according to claim 50, characterized in that:

said CMOS inverter circuit forms said output voltage by its input terminal being connected to its output terminal.

52. A semiconductor integrated circuit device according to claim 51, characterized by further comprising:

a voltage comparator circuit;

a first switch and a second switch provided for each of said plurality of CMOS inverter circuits, said first switch transferring an output voltage of a CMOS inverter circuit corresponding thereto to one input terminal of said voltage comparator circuit, said second switch transferring the output voltage to the other input terminal of said voltage comparator circuit; and

a control circuit for controlling said first switches and said second switches such that said voltage comparator circuit compares the respective output voltages of said plurality of CMOS inverter circuits with the output voltages of a plurality of other CMOS inverter circuits, respectively.

53. A semiconductor integrated circuit device according to claim 52, characterized in that:

said switch is a switch comprised of MOSFET.

54. A semiconductor integrated circuit device according to claim 53, characterized by comprising:

a first to a third switch provided for each of said plurality of CMOS inverter circuits; and

a control circuit for controlling said first to third switches,

wherein said first switch is disposed between an input terminal and an output terminal of a CMOS inverter circuit associated therewith;

said second switch is disposed between a common first circuit node and the input terminal of the CMOS inverter circuit associated therewith;

said third switch is disposed between the output terminal of the CMOS inverter circuit associated therewith and a common second circuit node; and

said control circuit controls said first to third switches such that two each of said plurality of CMOS inverter circuits are grouped into a set, and an input terminal and an output terminal of one of the CMOS inverter circuits are connected to output an output voltage from the one CMOS inverter, the output voltage of the one CMOS inverter circuit is supplied to an input terminal of the other CMOS inverter circuit through said first circuit node, and an output signal which is the result of determining a potential of the output voltage of said one CMOS inverter circuit is applied from the other CMOS inverter circuit to said second circuit node, with a logical threshold value voltage of the other CMOS inverter circuit being used as a reference voltage.

55. A semiconductor integrated circuit device according to claim 54, characterized in that;

said switch is a switch comprised of MOSFET.

56. A semiconductor integrated circuit device according to claim 54, characterized in that:

said CMOS inverter circuits and said first to third switches comprise elements which make up a CMOS gate array.

57. A semiconductor integrated circuit device according to claim 56, characterized in that:

said switch is a switch comprised of MOSFET.

58. A semiconductor integrated circuit device according to claim 54, characterized in that:

said plurality of CMOS inverter circuits are applied with a limited operating voltage when no operation is performed for determining the relation of magnitude in the electric parameter as said physical amount.

59. A semiconductor integrated circuit device according to claim 58, characterized in that:

said switch is a switch comprised of MOSFET.

60. A semiconductor chip characterized by comprising a built-in identification number generator circuit composed of a plurality of identification elements, each including:

a first inverter circuit;

a first switch disposed between an input terminal and an output terminal of said first inverter circuit;

a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit; and

an amplifier circuit which receives an output signal at an output terminal of said second inverter circuit,

wherein said identification number generator circuit generates identification number information based on an output signal of said amplifier circuit when said first switches of said plurality of identification elements are turned on.

61. A semiconductor chip according to claim 60, characterized in that:

said inverter circuits comprise CMOS inverter circuits;

said semiconductor chip further has a voltage forming circuit for forming a voltage which should be applied to the input terminal of said first inverter circuit when said first switch is turned off; and

said voltage forming circuit forms a voltage which is brought to a level at which an inversion due to aging changes of the output signal of said amplifier circuit is avoided based on the level of the output signal when said first switch is turned on.

62. A semiconductor chip according to claim 61, characterized in that:

said semiconductor chip includes a signal path for setting said voltage of said voltage generator circuit through said first and second inverter circuits;

said voltage generator circuit comprises a latch circuit which is set to form an output voltage at a low level in response to the output signal of said second inverter circuit which is on a high level side with respect to a logical threshold value thereof when said first switch is turned on, and to form the output voltage at a high level in response to the output signal of said second inverter circuit which is on a low level said with respect to the logical threshold value when said first switch is turned on.

63. A semiconductor chip according to claim 62, characterized in that:

said latch circuit is set in an output path of said amplifier circuit.

64. A semiconductor chip according to claim 60, characterized in that:

said first inverter circuit and second inverter circuit comprise CMOS inverter circuits;

a second switch is disposed between said first inverter circuit and second inverter circuit;

the second switch is disposed at an input terminal of each of the CMOS inverter circuits which comprise said first inverter circuit, second inverter circuit and amplifier circuit, respectively, for applying a potential on the high level side;

a third switch is disposed between said first inverter circuit and second inverter circuit;

said first switch is turned off, said second switch is turned on, and said third switch is turned off when said identification number circuit is inoperative to bring the input terminals of said first and second inverter circuits to the high level potential; and

said first switch and third switch are turned on, and said second switch is turned off when said identification number circuit is operative.

65. A semiconductor chip characterized by comprising a built-in identification number generator circuit composed of a plurality of identification elements, each including:

a first inverter circuit and a second inverter circuit;

a first switch disposed between an input terminal and an output terminal of each of said first inverter circuit and said second inverter circuit;

a second switch disposed between the output terminal of said first inverter and the input terminal of said second inverter circuit; and

an amplifier circuit including a third inverter circuit having an input terminal connected to the output terminal of said second inverter,

wherein said built-in identification number circuit generates an identification number comprised of first identification information generated from an output signal of said amplifier circuit including said third inverter circuit when said first switch of said inverter circuit is turned on, said first switch of said second inverter circuit is turned off, and said

second switch is turned on, and second identification information generated from the output signal of said amplifier circuit including said third inverter circuit when said first switch of said second inverter circuit is turned on, and said second switch is turned off.

66. A semiconductor chip according to claim 65, characterized in that;

said first inverter circuit and said second inverter circuit form a circuit sequence, and a plurality of circuit sequences are provided in a form in which said first inverter circuit and said second inverter circuit are arranged in correspondence,

the first switches corresponding to the plurality of circuit sequences are supplied with a common switch control signal, and output signals of said second inverter circuits in said plurality of circuit sequences are supplied to an input terminal of said third inverter circuit comprising said amplifier circuit through a third switch for selecting a desired circuit sequence in said plurality of circuit sequences.

67. A semiconductor chip according to claim 66, characterized by further comprising:

a fourth switch for interrupting an input signal, and a fifth switch for supplying a voltage on the high level side at the input of said first inverter circuit and said second inverter circuit,

wherein said fourth switch is turned off, and said fifth switch is turned on when said identification number circuit is inoperative.

68. A semiconductor chip characterized by comprising a built-in identification number circuit including:

an identification element sequence comprised of a plurality of unit elements each including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit, and a second switch disposed at the input terminal of said first inverter circuit, said unit elements being arranged in cascade through said second switches;

an amplifier circuit including a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit corresponded to a final stage of said identification element sequence;

a binary counter for counting a clock; and

a decoder for receiving a count output of said binary counter and disposed corresponding to said first switch and said second switch of each first inverter circuit in said identification element sequence,

wherein said identification number circuit is responsive to the count output of said binary counter to sequentially turn on said identification elements from the first circuit and turn off said second switches complementarily to said first switches to receive a plurality of identification information corresponding to said respective first inverter circuits in said identification element sequence from output signals of said amplifier circuit including said third inverter circuit to generate an identification number.

69. A semiconductor chip characterized by comprising a built-in identification number circuit including:

an identification element sequence comprised of a plurality of unit elements each including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit, and a second switch disposed at the input terminal of said first inverter circuit, said unit elements being arranged in cascade through said second switch;

an amplifier circuit including a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit corresponded to a final stage of said identification element sequence; and

a shift register having shift bits corresponding to said first switch and said second switch of each said first inverter in said identification element sequence,

wherein said identification number circuit is responsive to a shift operation of said shift register to sequentially turn on said first switches in said identification elements from the first circuit and turn off said second switches complementarily to said first switches to receive a plurality of identification information corresponding to said respective first inverter circuits in said identification element sequence from output signals of said amplifier circuit including said third inverter circuit to generate an identification number.

70. A semiconductor chip characterized by comprising a built-in identification number generator circuit composed of a plurality of identification elements, each including:

a first inverter circuit, and a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit;

a second inverter circuit having an input terminal connected to the output terminal of aid first inverter circuit; and

an amplifier circuit for amplifying a signal at an output of said second inverter circuit,

wherein said identification number circuit generates an identification number from an output signal of said amplifier circuit when said first switches in said plurality of identification elements are turned on.

71. A semiconductor chip characterized by comprising a built-in identification number circuit including:

an identification element sequence comprised of a plurality of unit elements each including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit, and a second switch disposed at the input terminal of said first inverter circuit, said unit elements being arranged in cascade through said second switch;

an amplifier circuit including a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit corresponded to a final stage of said identification element sequence;

a binary counter for counting a clock; and

a decoder for receiving a count output of said binary counter and disposed corresponding to said first switch and said second switch of each first inverter circuit in said identification element sequence,

wherein said identification number circuit is responsive to the count output of said binary counter to sequentially turn on said first switches in said identification elements from the first circuit and turn off said second switches complementarily to said first switches to receive a plurality of identification information corresponding to said respective first inverter circuits in said identification element sequence from output signals of said amplifier circuit including said third inverter circuit to generate an identification number.

72. A semiconductor chip characterized by comprising a built-in identification number circuit including:

an identification element sequence comprised of a plurality of unit elements each including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit, and a second switch disposed at the input terminal of said first inverter circuit, said unit elements being arranged in cascade through said second switch;

an amplifier circuit including a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit corresponded to a final stage of said identification element sequence; and

a shift register having shift bits corresponding to said first switch and said second switch of each said first inverter in said identification element sequence,

wherein said identification number circuit is responsive to a shift operation of said shift register to sequentially turn on said first switches in said identification elements from the first circuit and turn off said second switches complementarily to said first switches to receive a plurality of identification information corresponding to said respective first inverter circuits in said identification element sequence from output signals of said amplifier circuit including said third inverter circuit to generate an identification number.

73. A semiconductor integrated circuit device according to claim 72, characterized by further comprising:

a test circuit compatible with a JTAG plan,

wherein the identification number generated by said identification number circuit is outputted through an interface compatible with said JTAG standard.

74. A semiconductor integrated circuit device according to claim 72, characterized in that:

said identification number circuit, including said unit elements, said first switches and said second switches are designed and laid out using a soft IP technique.

75. A method for manufacturing a semiconductor integrated circuit device, characterized by using a soft IP technique to design and lay out an identification number circuit including:

an identification element sequence comprised of a plurality of unit elements each including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of said first inverter circuit, and a second switch disposed at the input terminal of said first inverter circuit, said unit elements being arranged in cascade through said second switch;

an amplifier circuit including a second inverter circuit having an input terminal connected to the output terminal of said first inverter circuit corresponded to a final stage of said identification element sequence; and

a shift register having shift bits corresponding to said first switch and said second switch of each said first inverter in said identification element sequence,

wherein said identification number circuit is responsive to a shift operation of said shift register to sequentially turn on said first switches in said identification elements from the first circuit and turn off said second switches complementarily to said first switches to receive a plurality of identification information corresponding to said respective first inverter circuits in said identification element sequence from output signals of said amplifier circuit including said third inverter circuit to generate an identification number.