Buried channel CMOS imager and method of forming same
First Claim
Patent Images
1. A photosensor for use in an imaging device, said photosensor comprising:
- a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer;
a buried doped region of a second conductivity type formed in said doped layer adjacent said first doped region, wherein said buried doped region is doped at a dopant concentration less that said first doped region; and
a gate formed over said buried doped region for gating an accumulation of charge into said first doped region.
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Abstract
A buried channel CMOS imager having an improved signal to noise ratio is disclosed. The buried channel CMOS imager provides reduced noise by keeping collected charge away from the surface of the substrate, thereby improving charge loss to the substrate. The buried channel CMOS imager thus exhibits a better signal-to-noise ratio. Also disclosed are processes for forming the buried channel CMOS imager.
51 Citations
152 Claims
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1. A photosensor for use in an imaging device, said photosensor comprising:
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a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer;
a buried doped region of a second conductivity type formed in said doped layer adjacent said first doped region, wherein said buried doped region is doped at a dopant concentration less that said first doped region; and
a gate formed over said buried doped region for gating an accumulation of charge into said first doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. An imaging device comprising:
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a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer, said first doped region forming a charge collection area in said imaging device;
a second doped region of said second conductivity type formed in said doped layer, said second doped region forming a diffusion region in said imaging device for receiving charge from said charge collection region;
a buried doped region of said second conductivity type formed in said doped layer adjacent said second doped region, wherein said buried doped region is doped at a dopant concentration less that said first doped region; and
a source follower transistor connected to said second doped region and wherein the gate of said source follower transistor is formed over said buried doped region. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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61. A photosensor for use in an imaging device, comprising:
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a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer;
a first buried doped region of said second conductivity type formed in said doped layer adjacent said first doped region, wherein said first buried doped region is doped at a dopant concentration less that of said first doped region;
a photogate over said buried doped region for gating the accumulation of charge stored into said first doped region;
a second doped region formed in said doped layer spaced from said first doped region for receiving charge transferred from said first doped region;
a second buried doped region of said second conductivity type formed in said doped layer adjacent said first doped region and said second doped region, wherein said second buried doped region is doped at a dopant concentration less that said first and second doped regions;
a transfer gate over said second buried doped region for transferring charge accumulated in said first doped region to said second doped region;
a reset transistor for periodically resetting said second doped region to a predetermined potential; and
an output transistor having a gate connected to said second doped region for providing a signal representing image charge transferred to said second doped region. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74)
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75. A CMOS imager system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor, said CMOS imaging system comprising;
a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer;
a buried doped region of a second conductivity type formed in said doped layer adjacent said first doped region, wherein said buried doped region is doped at a dopant concentration less that said first doped region; and
a photogate over said buried doped region for gating the accumulation of charge into said first doped region. - View Dependent Claims (76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
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88. A CMOS imager system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor, said CMOS imaging system comprising;
a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer, said first doped region forming a photocollection area in said imaging device;
a second doped region of a second conductivity type formed in said doped layer, said second doped layer forming a diffusion region in said imaging device;
a buried doped region of a second conductivity type formed in said doped layer adjacent said second doped region, wherein said buried doped region is doped at a dopant concentration less that said first doped region; and
a source follower transistor connected to said second doped region and wherein the gate of said source follower transistor is formed over said buried doped region. - View Dependent Claims (89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102)
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103. A CMOS imager system comprising:
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(i) a processor; and
(ii) a CMOS imaging device coupled to said processor, said CMOS imaging system comprising;
a doped layer of a first conductivity type formed in a substrate;
a first doped region of a second conductivity type formed in said doped layer;
a first buried doped region of a second conductivity type formed in said doped layer adjacent said first doped region, wherein said first buried doped region is doped at a dopant concentration less that said first doped region;
a photogate over said buried doped region for gating the accumulation of charge into said first doped region;
a second doped region formed in said doped layer spaced from said first doped region for receiving image charge transferred from said first doped region;
a second buried doped region of a second conductivity type formed in said doped layer adjacent said first doped region and said second doped region, wherein said second buried doped region is doped at a dopant concentration less that said first and second doped regions;
a transfer gate over said second buried doped region for transferring charge accumulated in said first doped region;
a reset transistor for periodically resetting said second doped region to a predetermined potential; and
an output transistor having a gate connected to said second doped region for providing a signal representing image charge transferred to said second doped region. - View Dependent Claims (104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121)
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122. An integrated circuit imager comprising:
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an array of pixel sensor cells formed in a substrate, each pixel sensor cell comprising at least one gating device, including a gate, for transferring charge within the cell and a buried doped region formed beneath said gating of employed sensor cell;
signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and
a processor for receiving and processing said output data representing said image.
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123. An integrated circuit CMOS imager comprising:
an array of pixel sensor cells formed in a doped layer of a substrate, each of said cells comprising;
a first doped region for accumulating image charge;
a second doped region for receiving and outputting image charge received from said first doped region;
a third doped region in said substrate formed at least between first and second doped regions;
signal processing circuitry electrically connected to the array for receiving image charge from the second doped regions and the array and for providing output data representing an image; and
a processor for receiving and processing said output data representing said image.
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124. A method of forming a CMOS imager substrate having improved surface charge loss properties, comprising the steps of:
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providing a semiconductor substrate having a doped layer of a first conductivity type; and
forming a shallow contiguous buried doped region of a second conductivity type beneath the entire surface of said semiconductor substrate. - View Dependent Claims (125, 126, 127, 128, 129, 130)
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131. A method of forming an imaging device, comprising the steps of:
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providing a semiconductor substrate having a doped layer of a first conductivity type;
forming a first doped region of a second conductivity type in the doped layer;
forming a second doped region of said second conductivity type in the doped layer spaced from said first doped region;
forming a third doped region of said second conductivity type in the doped layer spaced from said second doped region;
forming a buried doped region of said second conductivity type in said doped layer adjacent said first and second doped regions and adjacent said second and third doped regions, wherein said buried doped region is doped at a dopant concentration less than said first, second and third doped regions;
forming a photogate over said buried doped region adjacent said first doped region;
forming a transfer gate over said buried doped region between said second and said third doped regions;
forming a contact between said second doped region and a source follower transistor wherein the gate of said source follower transistor is formed over said buried doped region. - View Dependent Claims (132, 133, 134, 135, 136, 137, 138, 139, 140, 141)
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142. A method of forming an imaging device, comprising the steps of:
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providing a semiconductor substrate having a doped layer of a first conductivity type;
forming a first doped region of a second conductivity type in the doped layer;
forming a second doped region of said second conductivity type in the doped layer spaced from said first doped region;
forming a third doped region of said second conductivity type in the doped layer spaced from said second doped region;
forming a photogate over said first doped region;
forming a transfer gate over said second and said third doped regions;
forming a contact between said second doped region and a source follower transistor wherein the gate of said source follower transistor is over said substrate;
forming a buried doped region of said second conductivity type in said doped layer adjacent said first and second doped regions and adjacent said second and third doped regions and under said photogate, transfer gate and said source follower transistor gate, wherein said buried doped region is doped at a dopant concentration less than said first, second and third doped regions. - View Dependent Claims (143, 144, 145, 146, 147, 148, 149, 150, 151, 152)
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Specification
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Current AssigneeHoward E. Rhodes
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Original AssigneeHoward E. Rhodes
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InventorsRhodes, Howard E.
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current438/73
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CPC Class CodesH01L 27/14609 Pixel-elements with integra...H01L 27/14643 Photodiode arrays; MOS imagersH01L 27/14689 MOS based technologies
