Support structures for wirebond regions of contact pads over low modulus materials

• US 20040058520A1
• Filed: 09/20/2002
• Published: 03/25/2004
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG, International Business Machines Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Anderson, David, Barth, Hans-Joachim, Burrell, Lloyd G., Nye, Henry A. III, Chan, Joseph, Kemerer, Douglas, Crabbe, Emmanuel F.
• Granted Patent: US 6,908,841 B2
• Time in Patent Office: Days
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

Claims

1. A semiconductor device, comprising:

a workpiece comprising a contact pad region;

at least one integrated circuit formed within the workpiece;

a plurality of contact pads formed within the contact pad region, at least one contact pad being coupled to a signal of the at least one integrated circuit, the contact pads including a bond portion having a length and width;

a first metallization layer disposed over the workpiece, the first metallization layer including a plurality of first support structures beneath at least the bond portion of the contact pads, the first support structures having a top surface;

a first dielectric layer disposed between at least the first support structures;

a second metallization layer disposed over the first vias, the second metallization layer including a plurality of second support structures beneath at least the bond portion of the contact pads, the second support structures having a top surface and a bottom surface;

a plurality of first support vias coupled between the top surface of each first support structure and the bottom surface of an overlying second support structure;

a first low modulus dielectric layer disposed between the first support vias and the second support structures; and

a high modulus dielectric layer disposed over the first low modulus dielectric layer, wherein the plurality of contact pads are disposed over the high modulus dielectric layer.

2. The semiconductor device according to claim 1, wherein the first support structures comprise a plurality of first conductive lines running parallel to one another in a first direction along either the entire length or width of the contact pad bond portion.

3. The semiconductor device according to claim 2, wherein at least one of the first conductive lines is coupled to a signal line of an integrated circuit in the workpiece.

4. The semiconductor device according to claim 2, wherein the second support structures comprise a plurality of second conductive lines running parallel to one another in a second direction along either the entire width or length of the contact pad bond portion, the second direction being substantially perpendicular to the first direction, wherein the first support vias are disposed at the intersection of the first and second conductive lines.

5. The semiconductor device according to claim 4, further comprising at least one third conductive line disposed within the first metallization layer between two adjacent first conductive lines, wherein the third conductive line is coupled to a signal line of an integrated circuit in the workpiece.

6. The semiconductor device according to claim 4, further comprising at least one fourth conductive line disposed within the second metallization layer between two adjacent second conductive lines, wherein the fourth conductive line is coupled to a signal line of an integrated circuit in the workpiece.

7. The semiconductor device according to claim 2, wherein the second support structures comprise a plurality of second conductive lines running parallel to one another in the first direction along the entire length or width of the contact pad bond portion.

8. The semiconductor device according to claim 7, further comprising at least one third conductive line disposed within the first metallization layer between two adjacent first conductive lines, wherein the third conductive line is coupled to a signal line of an integrated circuit in the workpiece.

9. The semiconductor device according to claim 7, further comprising at least one fourth conductive line disposed within the second metallization layer between two adjacent second conductive lines, wherein the fourth conductive line is coupled to a signal line of an integrated circuit in the workpiece.

10. The semiconductor device according to claim 1, wherein the first support structures comprise a plurality of first discrete support pads, wherein the second support structures comprise a plurality of second discrete support pads disposed over the first discrete support pads, wherein the first support vias are disposed between adjacent first and second support pads.

11. The semiconductor device according to claim 10, wherein at least one of the first support pads is coupled to a signal line of an integrated circuit in the workpiece.

12. The semiconductor device according to claim 10, further comprising at least one first conductive line disposed between two adjacent first support pads, wherein the first conductive line is coupled to a signal line of an integrated circuit in the workpiece.

13. The semiconductor device according to claim 1, wherein the first dielectric layer comprises a low-K material.

14. The semiconductor device according to claim 1, further comprising:

a first high modulus dielectric film disposed over the first dielectric layer;

a third metallization layer disposed over the second metallization layer, the third metallization layer including a plurality of third support structures in at least the bond portion of the contact pads, the third support structures having a bottom surface;

a plurality of second support vias coupled between the top surface of each second support structure and the bottom surface of an overlying third support structure; and

a second low modulus dielectric layer disposed between the second support vias and the third support structures; and

a second high modulus dielectric film disposed over the first low modulus dielectric layer.

15. The semiconductor device according to claim 14, wherein the third support structures comprise a plurality of third conductive lines running in the first direction or a plurality of discrete support pads.

16. The semiconductor device according to claim 15, wherein at least one of the third support structures is coupled to a signal line of an integrated circuit in the workpiece.

17. The semiconductor device according to claim 15, further comprising at least one first conductive line disposed within the third metallization layer between two adjacent third support structures, wherein the first conductive line is coupled to a signal line of an integrated circuit in the workpiece.

18. The semiconductor device according to claim 14, wherein the first and second low modulus dielectric layers comprise low-K materials.

19. The semiconductor device according to claim 14, wherein the second support vias are disposed directly above the first support vias.

20. The semiconductor device according to claim 1, wherein the bond portion comprises an area, wherein each first support via comprises an area, wherein the total of all first support via areas in the bond portion comprises at least 7% of the area of the bond portion of the contact pads.

21. The semiconductor device according to claim 14, further comprising:

at least one fourth metallization layer disposed over the third metallization layer, each fourth metallization layer including a plurality of fourth support structures in at least the bond portion of the contact pads;

a plurality of third support vias coupled between the fourth support structures and the underlying third support structures or the fourth support structures;

at least one third low modulus dielectric layer disposed between the third support vias and the fourth support structures; and

a third high modulus dielectric film disposed between each third low modulus dielectric layer and an underlying second or third low modulus dielectric layer.

22. The semiconductor device according to claim 21, wherein each third support via resides directly above a first and second support via, and wherein the first, second and third support vias comprise a via support stack.

23. The semiconductor device according to claim 1, wherein the first dielectric layer comprises a low modulus material.

24. The semiconductor device according to claim 1, wherein the first dielectric layer comprises a high modulus material.

25. A semiconductor device, comprising:

a workpiece comprising a contact pad region, at least one integrated circuit being formed within the workpiece, the contact pad region comprising a plurality of contact pads each including a bond portion having a length and width, at least one of the contact pads being coupled to an integrated circuit;

a plurality of low modulus dielectric layers disposed over the workpiece;

a plurality of metallization layers formed within the low modulus dielectric layers, each metallization layer including a plurality of support structures beneath at least the bond portion of the contact pad region;

a plurality of support vias being coupled between each support structure of adjacent metallization layers;

a plurality of high modulus dielectric films, each film being disposed over a low modulus dielectric layer;

a first high modulus dielectric layer disposed over the top low modulus dielectric layer; and

at least one contact pad disposed over the first high modulus dielectric layer in the contact pad region, wherein the support vias within the low modulus dielectric layer reside directly above support vias in each underlying low modulus dielectric layer, to form a plurality of via support stacks within the low modulus dielectric layers.

26. The semiconductor device according to claim 25, wherein the support structures comprise a plurality of conductive lines running parallel to one another in a first direction along the entire length of the contact pad bond portion.

27. The semiconductor device according to claim 26, wherein at least one of the conductive lines is coupled to a signal line of an integrated circuit in the workpiece.

28. The semiconductor device according to claim 27, further comprising a signal-conducting line disposed within at least one metallization layer between two adjacent conductive lines, wherein the signal-conducting line is coupled to a signal line of an integrated circuit in the workpiece.

29. The semiconductor device according to claim 25, wherein the support structures in odd alternating low modulus dielectric layers comprise a plurality of first conductive lines running parallel to one another in a first direction along the entire length of the contact pad bond portion, and wherein the support structures in even alternating low modulus dielectric layers comprise a plurality of second conductive lines running parallel to one another in a second direction along the entire width of the contact pad bond portion, the second direction being substantially perpendicular to the first direction, wherein the support vias are disposed at the intersection of the first and second conductive lines.

30. The semiconductor device according to claim 29, further comprising a signal-conducting line disposed within at least one metallization layer between two adjacent first and/or second conductive lines, wherein the signal-conducting line is coupled to a signal line of an integrated circuit in the workpiece.

31. The semiconductor device according to claim 25, wherein the support structures comprise a plurality of discrete support pads.

32. The semiconductor device according to claim 31, wherein at least one of the support pads is coupled to a signal line of an integrated circuit in the workpiece.

33. The semiconductor device according to claim 31, further comprising at least one first conductive line disposed between two adjacent support pads within a single metallization layer, wherein the first conductive line is coupled to a signal line of an integrated circuit in the workpiece.

34. The semiconductor device according to claim 25, wherein the at least one low modulus dielectric layer comprises about 0.1 to 0.7 μ

m of low-K material.

35. The semiconductor device according to claim 25, wherein the high modulus dielectric film comprises about 200 Angstroms of silicon nitride, and wherein the first high modulus dielectric layer comprises about 0.5 to 2.5 μ

m of composite silicon dioxide and silicon nitride.

36. The semiconductor device according to claim 25, wherein the total support via area comprises at least 7% of the area of the bond portion of the contact pads.

37. The semiconductor device according to claim 25, further comprising a contact pad via extending through the first high modulus dielectric layer, wherein the contact pad via couples the contact pad to an underlying conductive line in an underlying metallization layer, the conductive line being connected to an integrated circuit.

38. The semiconductor device according to claim 25, wherein the plurality of support vias are formed in a low modulus dielectric layer.

39. The semiconductor device according to claim 25, wherein the plurality of support vias are formed in a high modulus dielectric layer.

40. A method of forming a semiconductor device, comprising:

providing a workpiece comprising a contact pad region, at least one integrated circuit being formed within the workpiece;

forming a plurality of low modulus dielectric layers over the workpiece;

forming a plurality of support vias within each low modulus dielectric layer, the support vias having a bottom end and a top end;

forming a plurality of support structures within each low modulus dielectric layer in at least the contact pad region, the support structures being coupled to the top ends of the support vias, wherein the bottom ends of the support vias are coupled to support structures in an underlying low modulus dielectric layer;

disposing a high modulus dielectric layer over the top low modulus dielectric layer; and

forming at least one contact pad in the contact pad region within the high modulus dielectric layer.

41. The method according to claim 40, wherein forming a plurality of support vias and forming a plurality of support structures comprise a single damascene process.

42. The method according to claim 40, wherein forming a plurality of support vias and forming a plurality of support structures comprise a dual damascene process.

43. The method according to claim 40, wherein forming the plurality of support structures comprises forming a plurality of conductive lines running parallel to one another in a first direction along at least the length of the contact pad bond portion.

44. The method according to claim 43, further comprising coupling at least one of the conductive lines to a signal line of an integrated circuit in the workpiece.

45. The method according to claim 43, further comprising forming a signal-conducting line within at least one metallization layer between two adjacent conductive lines, wherein the signal-conducting line is coupled to a signal line of an integrated circuit in the workpiece.

46. The method according to claim 40, wherein forming the support structures comprises forming support structures in odd alternating low modulus dielectric layers by disposing a plurality of first conductive lines parallel to one another in a first direction along at least the length of the contact pad bond portion and forming support structures in even alternating low modulus dielectric layers by disposing a plurality of second conductive lines parallel to one another in a second direction along at least the width of the contact pad bond portion, the second direction being substantially perpendicular to the first direction, wherein forming the support vias comprises disposing the support vias at the intersection of the first and second conductive lines.

47. The method according to claim 46, further comprising disposing a signal-conducting line within at least one metallization layer between two adjacent first or second conductive lines, and coupling the signal-conducting line to a signal line of an integrated circuit in the workpiece.

48. The method according to claim 40, wherein forming the support structures comprises forming a plurality of discrete support pads.

49. The method according to claim 48, further comprising coupling at least one of the support pads to a signal line of an integrated circuit in the workpiece.

50. The method according to claim 48, further comprising disposing at least one conductive line between two adjacent support pads within the metallization layer, wherein the conductive line is coupled to a signal line of an integrated circuit in the workpiece.

51. The method according to claim 40, further comprising disposing a high modulus dielectric film between each two adjacent low modulus dielectric layers.

52. The method according to claim 51, further comprising positioning the plurality of support vias over one another within each low modulus dielectric layer to form a via support stack.