Parallel electronic architecture comprising a plurality of processing units connected to a communication bus, and addressable by their functional capabilities

• US 20040059888A1
• Filed: 06/18/2003
• Published: 03/25/2004
• Est. Priority Date: 12/22/2000
• Status: Active Grant

• Current Assignee: Wany, S.A.
• Original Assignee: Wany, S.A.
• Inventors: Tremel, Laurent, Lavarec, Erwan
• Granted Patent: US 6,859,847 B2
• Time in Patent Office: Days
• US Class Current: 712/1
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

The parallel electronic architecture comprises a plurality of processor units (1a, 1b, . . . , 1n) connected to a communication bus and each adapted to execute one or more predefined tasks automatically. Each processor unit is configured so that each of its tasks is associated with a header, each processor unit is adapted to communicate with the other processor units using the following protocol: sending on the bus a message including a header characterizing a function, and possibly a frame consisting of one or more words, and each processor unit is adapted to decode each header on the bus and, as a function of the value of said header, either to ignore the message on the bus or to execute the task associated with the header of said message.

Claims

1. A parallel electronic architecture comprising a plurality of processor units (1a, 1b, . . . , 1n) connected to a communication bus and each adapted to execute automatically one or more predefined tasks, which architecture is characterized in that each processor unit is configured so that each of its tasks is associated with a header, each processor unit is adapted to communicate with the other processor units using the following protocol:

sending on the bus α

message comprising a header characterizing a function, and possibly a frame consisting of one or more words, and each processor unit is adapted to decode each header on the bus and, as a function of the value of said header, either to ignore the message on the bus or to execute the task associated with the header of said message.

2. An architecture according to claim 1, characterized in that a processor unit is adapted to load the message on the bus into memory before executing a task.

3. An architecture according to claim 1 or claim 2, characterized in that two or more processor units are configured with the same header.

4. An architecture according to claim 1 or claim 2, characterized in that a processor unit is adapted to execute a plurality of tasks and is configured so that each task is associated with a different header.

5. An architecture according to any one of claims 1 to 4, characterized in that the communication bus is a data bus comprising q parallel conductors (where q is an integer greater than or equal to 1) and each processor unit includes a data bus (6) of n bits (where n is an integer less than or equal to q) that is connected in parallel to the n first conductors of the communication bus.

6. An architecture according to claim 9, characterized in that a processor unit is adapted to send on the bus with the following serial format:

writing on the bus α

first word corresponding to the header and then writing successively each word constituting the frame of the message.

7. An architecture according to any one of claims 1 to 6, characterized in that a processor unit includes:

a processor (2) programmed to execute one or more separate tasks, the coding means adapted to validate or not a header in transit on the communication bus for the processor (2), and a memory (4) which is connected to the communication bus, is accessible in read mode by the processor (2), and loads a message on the communication bus under the control of the processor (2).

8. An architecture according to claim 7, characterized in that the decoding means include a validation memory (3) whose address port is connected to the communication bus, each header value on the communication bus corresponds to an address of said validation memory (3), and each address of said validation memory corresponding to a header stores header validation or non-validation data.

9. An architecture according to claim 8, characterized in that the output port of the validation memory (3) is connected to a port of the processor (2) dedicated to processing interrupts.

10. An architecture according to any one of claims 1 to 9, characterized in that it is of the multimaster/multislave type and the exchange of data on the communication bus is timed by the master processor unit that sent the message.